MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 998

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.8.7.2
To safely add a dTD, DCD must follow this procedure which manages the event where the device
controller reaches the end of the dTD list at the same time a new dTD is added to the end of the list.
Determine whether the link list is empty:
Case 1: Link list is empty
Case 2: Link list is not empty
32.8.7.3
After a dTD has been initialized and the associated endpoint primed, the device controller executes the
transfer upon the host-initiated request. The DCD is notified with a USB interrupt if the interrupt on
complete bit was set or alternately, the DCD can poll the endpoint complete register to find when the dTD
had been executed. After a dTD has been executed, DCD can check the status bits to determine success or
failure.
By reading the status fields of the completed dTDs, DCD can determine if the transfers completed
successfully. Success is determined with this combination of status bits:
32-170
8. Write dQH next pointer AND dQH terminate bit to 0 as a single 32-bit word operation.
9. Clear active and halt bit in dQH (in case set from a previous error).
10. Prime endpoint by writing 1 to correct bit position in the USB_ENDPTPRIME register.
1. Add dTD to end of linked list.
2. Read correct prime bit in the USB_ENDPTPRIME register - if 1 DONE.
3. Set ATDTW bit in USB_USBCMD register to 1.
4. Read correct status bit in USB_ENDPTSTATUS. (store in temporary variable for later)
5. Read ATDTW bit in the USB_USBCMD register.
6. Write ATDTW bit in USB_USBCMD register to '0'.
7. If status bit read in (3) is '1' DONE.
8. If status bit read in (3) is '0' then Goto Case 1: Step 1.
•
•
•
Check DCD driver to see if pipe is empty (internal representation of linked-list should indicate if
any packets are outstanding)
Active = 0
Halted = 0
Transaction Error = 0
If 0, goto 3.
If 1, continue to 6.
Executing A Transfer Descriptor
Transfer Completion
Multiple dTD can be completed in a single endpoint complete notification.
After clearing the notification, DCD must search the dTD linked list and
retire all dTDs have finished (active bit cleared).
MPC5125 Microcontroller Reference Manual, Rev. 2
CAUTION
Freescale Semiconductor