MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 323

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.3.2.3
The DRAM Command (DDR_COMMAND) register gives the option to send commands directly to the
DRAM. This register only operates when the command mode bit (CMD MODE, bit 3) is set in the
DDR_SYS_CONFIG register.
1
11.3.2.4
Freescale Semiconductor
DRAM_COMMAND
Address: Base + 0x0010
Address: Base + 0x0014
If CKE is turned off, it is turned off on the same clock cycle as when the command is being written to the DRAM.
Reset
Reset
Reset
Reset
W
W
W
W
R
R
[23:0]
R
R
Field
16
16
0
0
0
0
0
0
0
0
0
0
DRAM Command (DDR_COMMAND) Register
Compact Command Register (DDR_COMPACT_COMMAND)
Figure 11-12. Compact Command (DDR_COMPACT_COMMAND) Register
17
17
0
0
0
0
0
0
0
0
1
1
When the DDR_SYS_CONFIG[CMD MODE] bit is set, the value written to bits [23:0] of this register is
output on the DRAM address group with following mapping:
Note: The intended use of the command interface is to initialize the DRAM and to put the DRAM into or
• DRAM_ADDRESS[14:0] = DRAM_COMMAND[14:0]
• DRAM_ADDRESS[15] = 0
• if(DRAM_COMMAND[15] == 1) turn off CKE DRAM attribute bit
• DRAM_BA[2:0] = DRAM_COMMAND[18:16]
• DRAM_WEB = DRAM_COMMAND[19]
• DRAM_CAS = DRAM_COMMAND[20]
• DRAM_RAS = DRAM_COMMAND[21]
• DRAM_CS0 = DRAM_COMMAND[22]
• DRAM_CS1 = DRAM_COMMAND[23]
18
18
0
0
0
0
0
0
0
0
2
2
Figure 11-11. DRAM Command (DDR_COMMAND) Register
out of the self-refresh and power-down modes.
19
19
0
0
0
0
Table 11-10. DDR_COMMAND field descriptions
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
20
4
0
0
0
0
4
0
0
0
0
21
21
0
0
0
0
0
0
0
0
5
5
DRAM_COMPACT_COMMAND[15:0]
DRAM_COMMAND[15:0]
22
22
0
0
0
0
0
0
0
0
6
6
23
23
0
0
0
0
0
0
0
0
7
7
Description
24
24
8
0
0
0
0
8
0
0
0
0
25
25
9
0
0
0
0
9
0
0
0
0
DRAM_COMMAND[23:16]
10
26
10
26
0
0
0
0
0
0
0
0
1
11
27
11
27
0
0
0
0
0
0
0
0
12
28
12
28
0
0
0
0
0
0
0
0
Access: User read/write
Access: User write-only
13
29
13
29
0
0
0
0
0
0
0
0
DRAM Controller
14
30
14
30
0
0
0
0
0
0
0
0
11-15
15
31
15
31
0
0
0
0
0
0
0
0