MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 139

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.1.1
Features of the BDLC module include the following:
6.2
The BDLC module has two external pins.
6.3
6.3.1
The BDLC memory map is shown in
Freescale Semiconductor
J1850_RX
J1850_TX
(0xFF40_1400)
Name
BDLC_BASE
Offset from
•
•
•
•
•
•
•
•
•
•
•
•
0x02–0x03
0x00
0x01
0x04
0x05
SAE J1850 Class B data communications network interface compatible and ISO compatible for
low-speed (≤ 125 kbit/s) serial data communications in automotive applications
10.4 kbit/s Variable Pulse Width (VPW) bit format
Digital noise filter
Digital loopback mode
4× receive and transmit mode, 41.6 kbit/s supported
BREAK symbol generation Supported
Block mode receive and transmit supported
Collision detection
Hardware Cyclical Redundancy Check (CRC) generation and checking
Dedicated register for symbol timing adjustments
In-Frame Response (IFR) types 0, 1, 2, and 3 supported
Polling and CPU interrupt generation with vector lookup available
External Signal Description
Memory Map and Register Definition
Output
Features
Memory Map
Input
Port
1
BDLC Control Register 1 (BDLC_DLCBCR1)
BDLC State Vector Register (BDLC_DLCBSVR)
Reserved
BDLC Control Register 2 (BDLC_DLCBCR2)
BDLC Data Register (BDLC_DLCBDR)
The J1850_TX pin serves as the transmit output channel for the BDLC module
The J1850_RX pin serves as the receive input channel for the BDLC module
MPC5125 Microcontroller Reference Manual, Rev. 2
Table
Table 6-2. BDLC memory map
Table 6-1. Signal Properties
Register
6-2.
Function
Access
R/W
R/W
R/W
R
2
Reset Value
Byte Data Link Controller (BDLC)
0xC0
0x00
0x40
0x00
I/O
O
I
3
Reset
0
Section/Page
6.3.2.4/6-13
6.3.2.1/6-5
6.3.2.2/6-6
6.3.2.3/6-8
Pull Up
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6-3