MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 674

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power Management Control Module (PMC)
In this mode, bus snooping is disabled. The core waits until the snoop bus is idle before entering nap mode.
When the DDROFF bit is set in the PMC_PMCCR register, described in
Section 24.2.2.1, “PMC
Configuration Register (PMC_PMCCR),”
is set, the DRAM is put into self-refresh mode during nap
mode. Setting the DDROFF bit requires the DRAM controller to be configured for putting the DRAM in
self-refresh mode upon receipt of the request.
When putting the DRAM in self-refresh mode during nap mode, alternate masters (DIU, FEC, USB,
DMA) cannot access DRAM any more. If the DRAM does not enter self-refresh mode, alternate masters
can continue reading and writing from DRAM while the core is in a sleep mode.
To enter nap mode, the POW bit in the e300 MSR register must be set, then the COREFOFF bit in the
PMC_PMCCR register must be set, before setting the nap bit in an e300 system register (HID0[9] = 1).
The core returns to the full-power state upon receipt of an asynchronous interrupt, system management
interrupt, decrementer interrupt, hard or soft reset, or machine check input (mcp) signal. A return to
full-power state from the nap mode takes only a few processor clock cycles if the DRAM is not put in
self-refresh mode. If the DRAM is put in self-refresh mode, the time is dominated by the DRAM wakeup
time. When the core is in nap mode, another CSB master (JTAG or tester for MPC5125) may initiate CSB
transactions directly without sending an interrupt to the core in advance. A PMC interrupt can be used to
wakeup the core in this case if enabled (PMC_PMCER[INT1], see
Section 24.2.2.2, “PMC Event Register
(PMC_PMCER)”).
24.3.4
Sleep Mode
Sleep mode is an e300 core-only sleep mode. In this mode, the e300 enters sleep mode while the system
stays in full-powered mode. The e300 sleep mode reduces the core power consumption to a minimum by
disabling all core internal functional units.
In this mode, bus snooping is disabled. The core waits unit the snoop bus is idle before entering sleep
mode.
When the DDROFF bit in the PMC_PMCCR register is set, the DRAM is put into self-refresh mode during
sleep mode. Setting the DDROFF bit requires the DRAM controller to be configured for putting the
DRAM in self-refresh mode upon receipt of the request.
When putting the DRAM in self-refresh mode during sleep mode, alternate masters (DIU, FEC, USB,
DMA) cannot access DRAM any more. If the DRAM does not enter self-refresh mode, alternate masters
can continue reading and writing from DRAM, while the core is in a sleep mode.
To enter sleep mode, the POW bit in the e300 MSR register must be set, then the COREFOFF bit in the
PMC_PMCCR register must be set, before setting the sleep bit in an e300 system register (HID0[10] = 1).
In this mode, the system PLL, core external input clock (CSB_CLK), and e300 PLL are all maintained.
The core returns to the full-power state upon receipt of an asynchronous interrupt, system management
interrupt, hard or soft reset, or machine check input (mcp) signal. A return to full-power state from the
sleep mode takes only a few processor clock cycles if the DRAM is not put in self-refresh mode. If the
DRAM is put in self-refresh mode, the time is dominated by the DRAM wakeup time. When the core is in
sleep mode, another CSB master (JTAG or tester for MPC5125) may initiate CSB transfers directly
without sending an interrupt to the core in advance. A PMC interrupt can be used to wakeup the core in
MPC5125 Microcontroller Reference Manual, Rev. 2
24-10
Freescale Semiconductor