MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 912

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
queue head referenced by the USB_ASYNCLISTADDR register. Software must set queue head horizontal
pointer T-bits to a zero for queue heads in the asynchronous schedule.
32.6.4
The USB specification revision 2.0 requires that the frame boundaries (SOF frame number changes) of the
high-speed bus and the full- and low-speed bus(es) below USB 2.0 hubs be strictly aligned. Super-imposed
on this requirement is USB 2.0 hubs manage full- and low-speed transactions via a micro-frame pipeline
(see start- (SS) and complete- (CS) splits illustrated in
frame boundary model into the host controller interface schedule architecture creates tension (complexity
for both hardware and software) between the frame boundaries and the scheduling mechanisms required
to service the full- and low-speed transaction translator periodic pipelines.
The simple projection, as
scheduling on both the beginning and end of a frame. To reduce the complexity for hardware and software,
the host controller is required to implement a one micro-frame phase shift for its view of frame boundaries.
The phase shift eliminates the beginning of frame and frame-wrap scheduling boundary conditions.
The implementation of this phase shift requires the host controller use one register value for accessing the
periodic frame list and another value for the frame number value included in the SOF token. These two
values are separate, but tightly coupled. The periodic frame list is accessed via the USB_FRINDEX
register. The USB_FRINDEX[2:0] bits represent the micro-frame number. The SOF value is coupled to
the value of USB_FRINDEX[13:3]. USB_FRINDEX[13:3] and the SOF value are incremented based on
USB_FRINDEX[2:0]. The SOF must value be delayed from the USB_FRINDEX value by one
micro-frame. The one micro-frame delay yields a host controller periodic schedule and bus frame
boundary relationship as illustrated in
the periodic start and complete-split transactions for full-and low-speed periodic endpoints, using the
natural alignment of the periodic schedule interface.
Figure 32-54
frame boundaries. To aid the presentation, two terms are defined. The host controller's view of the
1-millisecond boundaries is called H-Frames. The high-speed bus's view of the 1-millisecond boundaries
is called B-Frames.
32-84
Micro-Frame
FS/LS Bus
Numbers
HS Bus
Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries
illustrates how periodic schedule data structures relate to schedule frame boundaries and bus
Figure 32-53. Frame Boundary Relationship Between HS Bus and FS/LS Bus
7
SS
Boundary
Frame
Figure 32-53
0
MPC5125 Microcontroller Reference Manual, Rev. 2
1
CS
Figure
illustrates, introduces frame-boundary wrap conditions for
2
CS
32-54. This adjustment allows software to trivially schedule
CS
3
SS
Figure
4
CS
32-53). A simple, direct projection of the
5
CS
6
CS
7
CS
Freescale Semiconductor
0
CS
1