MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 632

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NAND Flash Controller (NFC)
23.2
The NAND Flash Controller (NFC) interfaces standard NAND flash devices to the IC and hides the
complexities of accessing the NAND flash. It provides a glueless interface to both 8-bit and 16-bit NAND
flash parts with page sizes of 512 bytes, 2 KB, 4 KB, and 8 KB.
23.3
The NAND flash controller includes the following features:
23.4
This section describes the NFC external signals.
23.4.1
The following signals shown in
23-2
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•
•
•
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•
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Organization
— NAND flash interface: 8- or 16-bit
9 KB RAM buffer
— Memory mapped registers and SRAM buffer
Interface with NAND flash through NFC
— Supports all NAND flash products regardless of density/organization
— Supports flash device commands like page read, page program, reset, block erase, read status,
DMA
— Integrated DMA engine
— Two configurable DMA channels
ECC mode / Bypass ECC
— In ECC mode, NFC supports 4-, 6-, 8-, 12-, 16-, 24-, or 32-bit error correction.
— ECC mode can be bypassed.
Boot
— Boot from page size ≥ 2 KB flash (×8/×16) without extra control
I/O pins sharing support
— Allow sharing of the I/O pins with other memory controllers through special arbitration logic.
Overview
Features
External Signal Description
read id, copy-back, multiplane read/program, interleaved read/program, random input/output,
read in EDO mode, but not limited.
– Use DMA channel 1 only to read/write a page for both main and spare area of a page
– Use DMA channel 1 to read/write the main area of a page, and DMA channel 2 for the spare
Overview
area
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 23-1
are used to control the NAND flash device.
Freescale Semiconductor