MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 448

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

IIM/Fusebox
17.3.2.12 Fuse Bank 1 Data (IIM_FB1W1) Register
Figure 17-12
fields.
17.4
The IIM consists of a master controller, a fuse value shadow cache, and a set of registers to hold the values
of signals visible outside the module. Two 256-bit fuse banks are implemented on the MPC5125.
Program operations are done on a bit basis. For programming, the external FUSE programming supply
A
17.4.1
Fuse bank 1 (256 bits) is available for user data.
17-12
Address: Base + 0xC04 – 0xC7C
VDD_FUSEWR
Reset
Reset
DATA[7:0]
Field
W
W
R
R
Functional Description
16
0
0
0
0
0
Fuse Bank 1
shows the bits in the Fuse Bank 1 Data (IIM_FB1W1) register.
Reading these bits returns the fuse state (0 = unblown; 1 = blown) so long as IIM_FBAC1[FBRP] = 0
(unblown). Disallowed reads always return 0 and cause ERR[RPE] to be set. Writing these bits overrides the
values without modifying the fuse elements. Overriding is allowed so long as IIM_FBAC1[FBOP] = 0.
Disallowed attempts to override are ignored and cause ERR[OPE] to be set. The corresponding fuse elements
may be programmed (blown) using the fuse programming sequence, so long as IIM_FBAC1[FBWP] = 0.
Disallowed attempts to program fuses are ignored and cause ERR[WPE] to be set.
must be applied.
17
0
0
0
0
1
18
0
0
0
0
2
Figure 17-12. Fuse Bank 1 Data (IIM_FB1W1) Register
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 17-13. IIM_FB1W1 field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
—
24
8
0
0
—
25
9
0
0
—
10
26
0
0
Table 17-13
DATA[7:0]
—
11
27
0
0
Access: Supervisor read/write
—
12
28
0
0
Freescale Semiconductor
describes the bit
—
13
29
0
0
—
14
30
0
0
—
15
31
0
0