MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 927

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.6.7.5
After the host controller has idled itself using the empty schedule detection, it naturally activates and
begins processing from the periodic schedule at the beginning of each micro-frame. In addition, it may
have idled itself early in a micro-frame. When this occurs (idles early in the micro-frame), the host
controller must occasionally reactivate during the micro-frame and traverse the asynchronous schedule to
determine whether any progress can be made. Asynchronous schedule start events are defined to be:
32.6.7.6
The operation of the empty asynchronous schedule detection feature depends on the proper management
of the Reclamation bit in the USB_USBSTS register. The host controller tests for an empty schedule after
it fetches a new queue head while traversing the asynchronous schedule. The host controller sets the
Reclamation bit when an asynchronous schedule traversal start event occurs. The reclamation bit is also
set when the host controller executes a transaction while traversing the asynchronous schedule. The host
controller clears the reclamation bit when it finds a queue head with its H-bit set. Software should only set
a queue head's H-bit if the queue head is in the asynchronous schedule. If software sets the H-bit in an
interrupt queue head, the resulting behavior is undefined. The host controller may clear the reclamation bit
when executing from the periodic schedule.
32.6.8
This section describes the operational model for the NakCnt field defined in a queue head (see
Section 32.5.6, “Queue
is not required to be enforced by the host controller.
USB protocol has built-in flow control via the NAK response by a device. There are several scenarios,
beyond the Ping feature, where an endpoint may naturally NAK or NYET the majority of the time. An
example is the host controller management of the split transaction protocol for control and bulk endpoints.
All bulk endpoints (High- or Full-speed) are serviced via the same asynchronous schedule. The time
between the Start-split transaction and the first Complete-split transaction could be short (e.g., when the
endpoint is the only one in the asynchronous schedule). The hub NYETs (effectively NAKs) the
Complete-split transaction until the classic transaction is complete. This could result in the host controller
thrashing memory, repeatedly fetching the queue head and executing the transaction to the Hub, which
does not complete until after the transaction on the classic bus
completes.
There are two component fields in a queue head to support the throttling feature: a counter field (NakCnt),
and a counter reload field (RL). NakCnt is used by the host controller as one of the criteria to determine
whether or not to execute a transaction to the endpoint. There are two operational modes associated with
this counter:
Freescale Semiconductor
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•
When the host controller transitions from the periodic schedule to the asynchronous schedule. If
the periodic schedule is disabled and the asynchronous schedule is enabled, then the beginning of
the micro-frame is equivalent to the transition from the periodic schedule, or
The asynchronous schedule traversal restarts from a sleeping state.
Operational Model for NAK Counter
Asynchronous Schedule Traversal: Start Event
Reclamation Status Bit (USB_USBSTS Register)
Head”). Software should not use this feature for interrupt queue heads. This rule
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
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