MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 152

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6.3.2.6
The BDLC Rate Select Register (BDLC_DLCBRSR) determines the divider prescaler value for the MUX
interface clock (f
clocks.
Read: any time
Write: write only once.
6-16
Address: Base + 0x09
Reset
Table 6-10. BARD Values vs. Transceiver Delay and Transmitter Timing Adjustment (continued)
W
R
1
BARD Offset Bits BO[4:0]
The transmitter symbol timing adjustment is the same for binary and integer bus frequencies.
BDLC Rate Select Register (BDLC_DLCBRSR)
R7
0
0
bdlc
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
). Only integer multiples of the 1 MHz or 1.048576 MHz f
Figure 6-8. BDLC Rate Select Register (BDLC_DLCBRSR)
R6
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Corresponding Expected
Transceiver’s delays (µs)
R5
0
2
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R4
0
3
R3
0
4
Transmitter Symbol Timing
Adjustment (t
R2
0
5
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
bdlc
are supported as input
bdlc
Freescale Semiconductor
Access: User read/write
R1
1
0
6
)
R0
0
7