MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 875

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.2.4.22 Endpoint Flush (USB_ENDPTFLUSH) Register (Non-EHCI)
The Endpoint Flush (USB_ENDPTFLUSH) register is used only by the OTG module in device mode. This
register is not defined in the EHCI specification.
Freescale Semiconductor
Address: Base + 0x1B0
Reset
Reset
PERB
PETB
Field
W
W
R
R
16
0
0
0
0
0
Prime Endpoint Transmit Buffer. For each endpoint, a corresponding bit requests a buffer to prepare for a
transmit operation to respond to a USB IN/INTERRUPT transaction. Software should write a 1 to the
corresponding bit when posting a new transfer descriptor to an endpoint. Hardware automatically uses this bit
to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware
clears this bit when the associated endpoint(s) is (are) successfully primed.
Note: Hardware momentarily sets these bits during hardware re-priming operations when a dTD is retired,
PETB[3]—Endpoint #3
PETB[2]—Endpoint #2
PETB[1]—Endpoint #1
PETB[0]—Endpoint #0
Prime Endpoint Receive Buffer. For each endpoint, a corresponding bit requests a buffer to prepare for a
receive operation for when a USB host initiates a USB OUT transaction. Software should write a 1 to the
corresponding bit when posting a new transfer descriptor to an endpoint. Hardware automatically uses this bit
to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware
clears this bit when the associated endpoint(s) is (are) successfully primed.
Note: Hardware momentarily sets these bits during hardware re-priming operations when a dTD is retired,
PERB[3]—Endpoint #3
PERB[2]—Endpoint #2
PERB[1]—Endpoint #1
PERB[0]—Endpoint #0
17
0
0
0
0
1
Figure 32-35. Endpoint Initialization (USB_ENDPTPRIME) Register
and the dQH is updated.
and the dQH is updated.
18
0
0
0
0
2
Table 32-36. USB_ENDPTPRIME field descriptions
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
24
8
0
0
0
0
25
9
0
0
0
0
Universal Serial Bus Interface with On-The-Go
10
26
0
0
0
0
11
27
0
0
0
0
12
28
0
0
Access: User read/write
13
29
0
0
PERB
PETB
14
30
0
0
32-47
15
31
0
0