MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 303

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The register WB_MEM_ADDR (described in
(WB_MEM_ADDR)”) specifies the address in the memory to which the writeback data should be written.
Writing to this address triggers a writeback frame refresh. When enabled, a VSYNC_WB interrupt occurs
at the end of a writeback frame.
The writeback frame size is specified by the WB_SIZE register (see
Size Register
10.4.10 Color Bar Generation
For testing purposes, it is desirable to generate color bars within the DIU itself. This is achieved by setting
the DIU_MODE register to 4. The pattern produced is a simple one with eight vertical color bars. This
mode allows the user to verify that the DIU is operational without the need to interact with the system
memory. A basic color sequence is preloaded, but the user can overwrite the default values if needed. See
Section 10.3.3.20, “COLBAR Registers,”
The size of the bars is set by dividing the horizontal resolution by 8 using integer math. If the horizontal
resolution is not divisible by 8 exactly, not all color bars have the same width.
10.4.11 Interrupt Generation
The DIU generates interrupts through a single line controlled by the contents of two registers:
INT_STATUS (see
Section 10.3.3.19, “Interrupt Mask Register
read the INT_STATUS register to find the source of the interrupt. This read operation clears the register.
Six interrupt statuses are defined:
Freescale Semiconductor
Memory
Offset
•
•
0x00
0x08
0x10
0x18
0x20
VSYNC—Vertical Synchronization
VSYNC_WB—Vertical Synchronization for Writeback
(WB_SIZE)”).
In mode 2, the DIU works on the basis that the writeback frame completes
before the end of the display frame parallel to it (i.e. before the vertical front
porch). A WB_PEND interrupt can be generated (if enabled), indicating the
writeback operation did not complete in time.
R10
000
R2
G5
B0
B8
Section 10.3.3.18, “Interrupt Status Register
001
G0
G8
B3
R5
...
Table 10-42. writeback Pixel Format in Memory
MPC5125 Microcontroller Reference Manual, Rev. 2
010
G3
R0
B6
R8
...
for more information.
(INT_MASK)”). When an interrupt occurs, the host needs to
Section 10.3.3.13, “Writeback Plane Address Register
NOTE
Local Address [2:0]
011
B1
R3
G6
B9
...
100
G1
R6
G9
B4
...
(INT_STATUS)”) and INT_MASK (see
Section 10.3.3.12, “Writeback Plane
101
R1
G4
R9
B7
...
Display Interface Unit (DIU)
B10
110
G7
B2
R4
...
G10
111
G2
B5
R7
...
10-41