MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 329

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.4.2
11.4.3
This block decides what command to send to the DRAM controller next. There are four different
commands that can be sent to the DRAM to service incoming requests from the four incoming buses.
On every rising clock edge, the DRAM command engine first determines using parallel logic what is
highest priority pending precharge, activate, read and write command. Next, it decides which of these
commands to send to the DRAM.
The arbiters that make the decisions about what command to send next to the DRAM are aware of the
current state the DRAM is in. When arbitrating a command on the DRAM bus, the following information
is processed:
Freescale Semiconductor
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16-bit DRAM systems need to connected to the low order bits of the data bus.
(DQ[15:0], DQS[1:0], and DM[1:0])
order DRAM bit. Leave MSB’s unconnected if the DRAM has fewer address pins than the
controller.
DRAM bank address pins need to be connected starting with bit [0] and ending with the highest
order bank address bit. Leave MSB unconnected if the DRAM has fewer bank address pins than
the controller.
Set burst type to sequential
Burst length is always 16-byte. Means 4-beat bursts in a 32-bit system, 8-beat burst in a 16-bit
system
Set CAS latency to lowest value DRAM can tolerate at intended speed, and then set write latency
and read latency accordingly.
Set posted CAS additive latency to 0
Controller never uses auto-precharge on read or write.
Configure DQS operation for single-ended operation.
RTT and output drive strength configuration depends on electrical characteristics.
Precharge
Activate
Read
Write
For each bank, if it is precharged or not
For each incoming request, if it hits in an already active bank or not
For each bank, if the DRAM currently can accept a precharge command to it
For each bank, if the DRAM currently can accept an activate command to it
For each bank, if the DRAM currently can accept a read command to it
Row/column address pins need to be connected starting with bit [0] and ending with the highest
Programming DRAM Device Internal Configuration Register
DRAM Command Engine
MPC5125 Microcontroller Reference Manual, Rev. 2
DRAM Controller
11-21