MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 558

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LocalPlus Bus Controller (LPC)
21.2.1.2.7
The EMB Share and Wait Count (LPC_EMB_SC) register configures the EMB arbiter and belongs to the
LPC functionality.
21.2.1.2.8
The EMB Pause Control (LPC_EMB_PC) register configures the EMB arbiter and belong to the LPC
functionality.
21-18
EMB_SHARE_COUNT This 16-bit value controls the length of the time slot assigned to NFC transactions before an SCLPC or
Address: Base + 0x11C
BYTES DONE BYTES DONE is updated dynamically by the SCLPC state machine to represent the actual number of bytes
NFC_WAIT_COUNT
LPC_WAIT_COUNT
Reset
Reset
Field
W
W
R
R
Field
16
0
0
0
0
EMB Share and Wait Count (LPC_EMB_SC) Register
EMB Pause Control (LPC_EMB_PC) Register
transmitted at a given point in time. At the normal conclusion of a packet, the BYTES DONE field should match
the PACKET_SIZE field.
17
0
0
1
Figure 21-17. EMB Share and Wait Count (LPC_EMB_SC) Register
CSB LPC (if the LPC_P bit is set in the EMB pause control register) request starts to pause the other
modules.
This 5-bit value controls how long the bus remains assigned to NFC after the bus goes idle.
This 5-bit value controls how long the bus remains assigned to LPC after the bus goes idle.
NFC_WAIT_COUNT
18
0
0
2
19
0
0
Table 21-17. LPC_SCLPC_BD field descriptions
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 21-18. LPC_EMB_SC field descriptions
20
4
0
0
21
0
0
5
22
EMB_SHARE_COUNT
0
0
6
23
0
0
7
Description
Description
24
8
0
0
0
25
9
0
0
10
26
0
0
11
27
0
0
LPC_WAIT_COUNT
12
28
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
14
30
0
0
15
31
0
0