MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 986

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
Both USB controllers support as many as four bidirectional endpoints, including the control endpoint. The
DCD can enable, disable, and configure each endpoint.
Each endpoint direction is essentially independent and can be configured with differing behavior in each
direction. For example, the DCD can configure endpoint 1-IN to be a bulk endpoint and endpoint 1-OUT
to be an isochronous endpoint. This helps to conserve the total number of endpoints required for device
operation. The only exception is that control endpoints must use both directions on a single endpoint
number to function as a control endpoint. Endpoint 0 is, for example, is always a control endpoint and uses
the pair of directions.
Each endpoint direction requires a queue head allocated in memory. If the maximum of four endpoint
numbers, one for each endpoint direction the device controller uses, eight queue heads are required. The
operation of an endpoint and use of queue heads are described later in this document.
32.8.4.1
After hardware reset, all endpoints except endpoint zero are uninitialized and disabled. The DCD must
configure and enable each endpoint by writing to configuration bit in the USB_ENDPTCTRLn register.
Each 32-bit USB_ENDPTCTRLn is split into an upper and lower half. The lower half of
USB_ENDPTCTRLn configures the receive or OUT endpoint and the upper half also configures the
corresponding transmit or IN endpoint. Control endpoints must be configured the same in both the upper
and lower half of the USB_ENDPTCTRLn register otherwise the behavior is undefined. The following
table shows how to construct a configuration word for endpoint initialization.
32.8.4.2
There are two occasions where the USB controller may need to return to the host a STALL condition
The first occasion is the functional stall, which is a condition set by the DCD as described in the USB 2.0
device framework (chapter 9). A functional stall is used only on non-control endpoints and can be enabled
in the device controller by setting the endpoint stall bit in the USB_ENDPTCTRLn register associated with
the given endpoint and the given direction. In a functional stall condition, the device controller continues
to return STALL responses to all transactions occurring on the respective endpoint and direction until the
endpoint stall bit is cleared by the DCD.
A protocol stall, unlike a function stall, used on control endpoints is automatically cleared by the device
controller at the start of a new control transaction (setup phase). When enabling a protocol stall, the DCD
32-158
Endpoint Initialization
Stalling
Data Toggle Reset
Data Toggle Inhibit
Endpoint Type
Endpoint Stall
Table 32-90. Device Controller Endpoint Initialization
MPC5125 Microcontroller Reference Manual, Rev. 2
Field
1
0
00 — Control
01 — Isochronous
10 — Bulk
11 — Interrupt
0
Value
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