MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 665

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 24
Power Management Control Module (PMC)
24.1
This chapter describes the power management control (PMC) module. The PMC is responsible for
entering and exiting the low-power mode.
24.1.1
The PMC module includes the following features:
24.2
24.2.1
Table 24-1
Freescale Semiconductor
(0xFF40_1000)
PMC_BASE
Offset from
•
•
•
•
•
•
0x18–0xFF
0x0C
0x00
0x04
0x08
0x10
0x14
Causes the e300 Power Architecture core to enter low-power mode (Nap or Sleep) after the
coherent system bus (CSB) is idle and DRAM controller is idle
Causes the DRAM controller to enter and exit low-power (self-refresh) mode
Optional interrupt when exiting low-power mode (Nap or Sleep)
Exit low-power mode when the Power Architecture core is ready
Enter and exit Deep Sleep mode (system OSC, system PLL, and e300 core PLL are put in
low-power standby mode)
Support e300 core PLL change and system clock divide ratio (SYS_DIV) copy mode
Introduction
Memory Map and Register Definition
shows the register memory map for the PMC module.
Features
Memory Map
1
PMC Configuration Register (PMC_PMCCR)
PMC Event Register (PMC_PMCER)
PMC Mask Register (PMC_PMCMR)
PMC CORE_PLL Shadow Register (PMC_PMCSR)
PMC Wakeup Source Enable Register (PMC_PMCWSE)
PMC Wakeup Source Polarity Register (PMC_PMCWSP)
Reserved
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 24-1. PMC memory map
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_00FF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset Value
Section/Page
24.2.2.1/24-2
24.2.2.2/24-3
24.2.2.3/24-4
24.2.2.4/24-5
24.2.2.5/24-5
24.2.2.6/24-6
24-1