MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 820

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Software Watchdog Timer (WDT)
29.2.2.3
The Software Watchdog Service Register (WDT_SWSRR) is shown in
enabled, it must be periodically reset. This is accomplished in applications software by writing the special
service sequence of 0x556C followed by 0xAA39 to the WDT_SWSRR register before the watchdog
counter decrements to 0x0000. If the WDT_SWSRR register is not serviced before the timeout, the
watchdog timer generates a system reset or MCP interrupt.
Both writes must occur before the timeout in the order listed; however, any number of instructions can be
executed between the two writes. Writing any value other than 0x556C or 0xAA39 to the WDT_SWSRR
register resets the servicing sequence. Both values must be written to keep the watchdog timer from
decrementing to 0x0000. Reset initializes the WDT_SWSRR[WS] field to 0x0000. WDT_SWSRR can be
written at any time, but returns all 0s when read.
29-4
Address: Base + 0xHHHH
Address: Base + 0x0E
Reset
Reset
Reset
SWCN
Field
W
W
W
R
R
R
16
0
0
1
0
0
0
0
Software Watchdog Service Register (WDT_SWSRR)
Software watchdog count. The read-only WDT_SWCNR[SWCN] field reflects the current value in the
watchdog counter. Writing to the WDT_SWCNR register has no effect, and write cycles are terminated
normally. Reset initializes the WDT_SWCNR[SWCN] field to 0xFFFF.
Note: Reading the 16 LS bits of 32-bit WDT_SWCNR register with two 8-bit reads is not guaranteed to return
17
0
0
1
0
0
1
1
Figure 29-3. Software Watchdog Service Register (WDT_SWSRR)
a coherent value. Always use a half-word or word access to read this register.
Figure 29-2. Software Watchdog Count Register (WDT_SWCNR)
18
0
0
1
0
0
2
2
19
0
0
1
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 29-3. WDT_SWCNR field descriptions
20
4
0
0
1
4
0
0
21
0
0
1
0
0
5
5
22
0
0
1
0
0
6
6
23
0
0
1
0
0
7
7
SWCN
Description
WS
24
8
0
0
1
8
0
0
25
9
0
0
1
9
0
0
10
26
10
0
0
1
0
0
Figure
11
27
11
0
0
1
0
0
29-3. After the WDT is
12
28
12
0
0
1
0
0
Freescale Semiconductor
Access: User write-only
Access: User read-only
13
29
13
0
0
1
0
0
14
30
14
0
0
1
0
0
15
31
15
0
0
1
0
0