MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 626

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MSCAN
22.4.8.2
In initialization mode, any ongoing transmission or reception is immediately aborted and synchronization
to the bus is lost potentially causing CAN protocol violations. To protect the CAN bus system from fatal
consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state.
In initialization mode, the MSCAN is stopped. However, interface registers can continue to be accessed.
This mode resets the CANTCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ,
CANTAAK, and CANTBSEL registers to their default values. In addition, it enables the configuration of
the CANBTR0 and CANBTR1 bit timing registers, CANIDAC, and the CANIDAR and CANIDMR
message filters. See
description of the initialization mode.
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by
using a special handshake mechanism. This handshake causes additional synchronization delay (see
Section Figure 22-41., “Initialization Request/Acknowledge
If there is no message transfer ongoing on the CAN bus, the minimum delay is two additional bus clocks
and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK
flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ)
to go into initialization mode.
22.4.8.3
The MSCAN is in power down mode
22-48
MSCAN Initialization Mode
MSCAN Power Down Mode
Ensure the MSCAN is not active when initialization mode is entered. The
recommended procedure is to bring the MSCAN into sleep mode
(SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the
CANCTL0 register. Otherwise, the abort of an ongoing message can cause
an error condition and can have an impact on the other bus devices.
The Power Architecture cannot clear the INITRQ bit before initialization
mode (INITRQ = 1 and INITAK = 1) is active.
Power Architecture Clock Domain
Power Architecture
Init Request
Section 22.3.2.1, “MSCAN Control 0 Register (CANCTL0),”
INITAK
Flag
Figure 22-41. Initialization Request/Acknowledge Cycle
MPC5125 Microcontroller Reference Manual, Rev. 2
INITRQ
sync.
INITAK
(Table
22-33) when the Power Architecture is in deep sleep mode
NOTE
NOTE
SYNC
SYNC
Cycle”).
CAN Clock Domain
sync.
INITRQ
INITAK
INIT
Flag
for a detailed
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