MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 144

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6.3.2.3
The BDLC Control Register 2 (BDLC_DLCBCR2) controls transmitter operations of the BDLC module.
6-8
Address: Base + 0x04
SMRST
Reset
Field
Field
I[3:0]
W
R
SMRST
BDLC Control Register 2 (BDLC_DLCBCR2)
Interrupt State Vector (with priority from low to high)
0000 No interrupt pending
0001 Received EOF.
0010 Received IFR byte.
0011 Rx data register full.
0100 Tx data register empty.
0101 Loss of arbitration.
0110 CRC error.
0111 Symbol invalid or out of range.
1000 Reserved.
State Machine Reset
You can use this bit to reset the BDLC state machines to an initial state after the you put the off-chip analog
transceiver in loop back mode.
0 Clearing SMRST after it has been set causes the generation of a state machine reset. After SMRST is
1 Setting SMRST arms the state machine reset generation logic. Setting SMRST does not affect BDLC
0
0
cleared, the BDLC requires the bus to be idle for a minimum of an EOF symbol time before allowing the
reception of a message. The BDLC requires the bus to be idle for a minimum of an inter-frame separator
symbol (IFS) time before allowing any message to be transmitted.
module behavior in any way.
DLOOP
Figure 6-4. BDLC Control Register 2 (BDLC_DLCBCR2)
1
1
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 6-5. BDLC_DLCBSVR field descriptions
Table 6-6. BDLC_DLCBCR2 field descriptions
.
4XE
0
2
NBFS
0
3
Description
Description
TEOD
0
4
TSIFR
0
5
TMIFR1
Freescale Semiconductor
Access: User read/write
0
6
TMIFR0
0
7