MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 411

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 15
General Purpose Timers (GPT)
15.1
The MPC5125 provides two General Purpose Timer (GPT) modules. Each General Purpose Timer (GPT)
provides eight independent timer channels that perform general purpose I/O (GPIO), input capture, output
compare, pulse width modulation and internal CPU timer functions. An external I/O pin is associated with
each Timer Channel. A separate 16-bit prescaler and 16-bit counter is associated with each timer channel,
thus achieving a range of 32 bits (but only 16-bit resolution).
Eight general-purpose timer (GPT) pins are configurable for:
15.1.1
15.1.1.1
In Input Capture mode, the I/O pin is an input. Two counters are used for each timer channel in this mode.
The first counter is the Internal counter and the second is the up/down counter. After enabled, when
specified capture event occurs (rising edge, falling edge, either edge, or pulse—two consecutive edges),
the internal counter value is latched in the status register. If enabled, a CPU interrupt is generated. The
input capture function has the following submodes, which are controlled by the ICM bits in the GPT
Enable and Mode Select (GPT_MODE) register (see
(GPT_MODE)
Freescale Semiconductor
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Input capture
Output compare
Pulse width modulation (PWM) output
Simple GPIO
Internal CPU timer
Normal input capture mode. Only internal counter is active.
Up submode as well as normal input capture submode. Both up/down counter and internal counter
are active.
Updown submode as well as input capture submode. Both counters are active. A pair of timer
channels are used to implement this mode.
Rotary counter as well as input capture counter mode.Both counters are active. A pair of timer
channels are used to implement this mode.
When changing from one submode into another submode, the TIMER should be disabled first.
Introduction
Modes of Operation
Input Capture
Registers”).
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 15.2.1.1, “GPT0–7 Enable and Mode Select
15-1