MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 917

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.6.6.2
A client buffer request to an isochronous endpoint may span 1 to N micro-frames. When N is larger than
one, system software may have to use multiple iTDs to read or write data with the buffer (if N is larger
than eight, it must use more than one iTD).
Figure 32-56
periodic schedule (the periodic frame list and a set of iTDs). On the right of
description of its request. The description includes a buffer base address plus additional annotations to
identify which portions of the buffer should be used with each bus transaction. In the middle of
Figure 32-56
iTD can be initialized to service as many as 24 transactions, organized into eight groups of as many as three
transactions each. Each group maps to one micro-frame's worth of transactions. The EHCI controller does
not provide per-transaction results within a micro-frame. It treats the per-micro-frame transactions as a
single logical transfer. On the left of
establishes references from the appropriate locations in the frame list to each of the appropriate iTDs. If
the buffer is large, system software can use a small set of iTDs to service the entire buffer. System software
can activate the transaction description records (contained in each iTD) in any pattern required for the
particular data stream.
Freescale Semiconductor
•
•
The endpoint is an OUT and Transaction n Length goes to zero before all the Mult transactions
have executed (ran out of data), or
The endpoint is an IN and the endpoint delivers a short packet, or an error occurs on a transaction
before Mult transactions have been executed. The end of micro-frame may occur before all of the
transaction opportunities have been executed. When this happens, the transfer state of the transfer
description is advanced to reflect the progress that was made, the result written back to the iTD and
the host controller proceeds to processing the next micro-frame.
Software Operational Model for iTDs
illustrates the simple model of how a client buffer is mapped by system software to the
are the iTD data structures used by the system software to service the client request. Each
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 32-56
is the host controller’s frame list. System software
Universal Serial Bus Interface with On-The-Go
Figure 32-56
is the client
32-89