MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 958

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
A subset of the same mechanisms employed by full- and low-speed interrupt queue heads are employed
in siTDs to schedule and track the portions of isochronous split transactions. The following fields are
initialized by system software to instruct the host controller when to execute portions of the split
transaction protocol:
There exists a one-to-one relationship between a high-speed isochronous split transaction (including all
start- and complete-splits) and one full-speed isochronous transaction. An siTD contains (amongst other
things) buffer state and split transaction scheduling information. An siTD's buffer state always maps to one
full-speed isochronous data payload. This means that for any full-speed transaction payload, a single
siTD's data buffer must be used. This rule applies to both IN an OUTs. An siTD's scheduling information
usually also maps to one high-speed isochronous split transaction. The exception to this rule is the
H-Frame boundary wrap cases mentioned above.
The siTD data structure describes at most, one frame's worth of high-speed transactions and that
description is strictly bounded within a frame boundary. At the top of
full-speed transaction footprints for the boundary scheduling cases described above. In the middle are
32-130
•
•
•
•
•
Although the scheduling of the split transaction may take two data structures, all of the
complete-splits for each full-speed IN isochronous transaction must use only one data pointer. For
this reason, siTDs contain a back pointer.
Software must never schedule full-speed isochronous OUTs across an H-Frame boundary.
Case 2b: This case can only occur for a large isochronous IN. It is the only allowed scenario where
a start-split and complete-split for the same endpoint can occur in the same micro-frame. Software
must enforce this rule by scheduling the large transaction first. Large is defined to be anything
larger than 579 byte maximum packet size.
SplitXState. This is a single bit residing in the status field of an siTD (see
used to track the current state of the split transaction. The rules for managing this bit are described
in
Frame S-mask. This is a bit-field wherein system software sets a bit corresponding to the
micro-frame (within an H-Frame) that the host controller should execute a start-split transaction.
This is always qualified by the value of the SplitXState bit. For example, referring to the IN
example in case one of
that if the siTD is traversed by the host controller, the SplitXState indicates Do Start Split, and the
current micro-frame as indicated by USB_FRINDEX[2:0] is 0, then execute a start-split
transaction.
Frame C-mask. This is a bit-field where system software sets one or more bits corresponding to the
micro-frames (within an H-Frame) that the host controller should execute complete-split
transactions. The interpretation of this field is always qualified by the value of the SplitXState bit.
For example, referring to the IN example in case one of
value of 0b 0011_1100 indicating that if the siTD is traversed by the host controller, the SplitXState
indicates Do Complete Split, and the current micro-frame as indicated by USB_FRINDEX[2:0] is
2, 3, 4, or 5, then execute a complete-split transaction.
Back Pointer. This field in an siTD is used to complete an IN split-transaction using the previous
H-Frame's siTD. This is only used when the scheduling of the complete-splits span an H-Frame
boundary.
Section 32.6.11.3.3, “Split Transaction Execution State Machine for Isochronous Transactions.”
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure
32-68, the S-mask would have a value of 0b0000_0001 indicating
Figure
Figure 32-69
32-68, the C-mask would have a
Table
are examples of the
Freescale Semiconductor
32-53). This bit is