MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 695

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.4.1.8
The read-only IPCR register shows the current state and change-of-state for the modem control input port.
Freescale Semiconductor
Address: Base + 0x18
Address: Base + 0x18
Field
SYNC
Reset
Reset
Field
TB
W
W
R
R
Input Port Change Register (IPCR)
SYNC
AC97 (0:19). Transmit data. AC97 data must be written one complete sample at a time, where all samples
except time slot #0 are 20 bits. Time slot #0 data is in bits 0:15.
0 RB[0:19] is not the first sample in the frame.
1 RB[0:15] is the first sample in a new frame. The number 0 slot is called the TAG slot.
The bits [21:31] are reserved at this mode.
AC97 (0:19). Transmit data. AC97 data for the expected time slots (3 to 12). The lower 20 bits contain the valid
data word.
UART/Codec8 (0:31). Transmit data. For these modes, data can be written one, two, or four bytes at a time.
For one byte at a time, all bytes must be written to bits 0:7. For two bytes at a time, data must be written to bits
0:15. Lower-bit data is stored before upper-bit data.
Codec16 (0:31). Transmit data. For these modes, data can be written two or four bytes at a time. For 2 bytes
at a time, data must be written to bits 0:15. Lower-bit data is stored before upper-bit data.
Codec24 (0:23). Transmit data. For these modes, data must be written four bytes at a time. The lower 24 bits
contain the valid data word.
Codec32 (0:31). Transmit data. For these modes, data must be written four bytes at a time.
Codec. Sync detected.
0 Has not detected sync.
1 Detected sync (Frame = 1 in Codec Modes or Sync = 1 in AC97 mode).
Other Modes. Reserved.
A read access to this register clears the SYNC bit
0
0
0
0
0
Figure 25-19. Input Port Change Register for UART Modes (IPCR)
Figure 25-20. Input Port Change Register for Codec Mode (IPCR)
1
0
0
1
0
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 25-13. IPCR field descriptions
Table 25-12. TB field descriptions
D_DCD
D_DCD
0
0
2
2
D_CTS
D_CTS
0
0
3
3
Description
Description
0
0
0
0
4
4
0
0
0
0
Programmable Serial Controller (PSC)
5
5
Access: User read-only
DCD
Access: User read-only
DCD
0
0
6
6
CTS
CTS
0
0
7
7
25-17