MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 360

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.1.3
The primary operational modes are described in this section.
14-4
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Programmable maximum frame length supports IEEE 802.1 VLAN tags and priority
Support for full-duplex operation (200 Mbit/s throughput) with a minimum system clock rate of
50 MHz
Support for half-duplex operation (100 Mbit/s throughput) with a minimum system clock rate of
25 MHz
Retransmission from transmit FIFO following a collision (no processor bus utilization)
Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no processor bus utilization)
— Address recognition
— Frames with broadcast address may always be accepted or always be rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
Full- and half-duplex operation
This is determined by the FDEN bit in the ETH_X_CNTRL register. Full-duplex mode is intended
for use on point-to-point links between switches or end node to switch. Half-duplex mode is used
in connections between an end node and a repeater or between repeaters.
Full-duplex flow control is an option that may be enabled in full-duplex mode. Refer to the
RFC_PAUSE and TFC_PAUSE bits in
Register,”
Section 14.6.4, “Full-Duplex Flow Control,”
10 Mbit/s and 100 Mbit/s MII interface operation
The MAC-PHY interface operates in MII mode by asserting the MII_MODE bit in the
ETH_R_CNTRL register. The MII is the media-independent interface defined by the 802.3
standard for 10/100 Mbit/s operation.
The speed of operation is determined by the TX_CLK and RX_CLK pins, which are driven by the
transceiver. The transceiver auto-negotiates the speed or may be controlled by software via the
serial management interface (MDC/MDIO pins) to the transceiver. Refer to the ETH_MII_DATA
and ETH_MII_SPEED register descriptions as well as the section on the MII for a description of
how to read and write registers in the transceiver via this interface.
10 Mbit/s and 100 Mbit/s RMII interface operation
The reduced media independent interface (RMII) is a low cost alternative to the IEEE 802.3 MII
standard. This interface provides the functionality of the MII interface on a total of 8 pins instead
of 18. The RMII interface for 10/100 Ethernet MAC-PHY interface was defined by an industry
consortium and is not currently included in the IEEE 802.3 standard. The RMII_MODE bit in
ETH_R_CNTRL register controls this functionality. If this bit and MII_MODE are enabled, then
Modes of Operation
the FCE bit in
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 14.3.5.10, “Receive Control (ETH_R_CNTRL) Register,”
Section 14.3.5.12, “Transmit Control (ETH_X_CNTRL)
for more details.
Freescale Semiconductor
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