MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 819

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
29.2.2.2
The Software Watchdog Count Register (WDT_SWCNR), shown in
watchdog counter value. WDT_SWCNR is a read-only register. Writing to the WDT_SWCNR register has
no effect and terminates without transfer error exception.
Freescale Semiconductor
Address: Base + 0x04
On reset, SWEN is set to 1. After reset, the WDT is enabled.
Reset
Reset
SWTC
SWEN
SWPR
SWRI
Field
W
W
R
R
16
0
0
0
0
Software Watchdog Count Register (WDT_SWCNR)
Software watchdog time count. The SWTC field contains the modulus that is reloaded into the watchdog
counter by the special service sequence. When a new value is loaded into WDT_SWCRR[SWTC], WDT is
not updated until the special service sequence is written to the WDT_SWSRR register. If
WDT_SWCRR[SWEN] is loaded with 0, the modulus counter does not count. The new value is also used at
the next and all subsequent reloads. Reading the WDT_SWCRR register returns the value in the
WDT_SWCRR. Reset initializes the WDT_SWCRR[SWTC] field to 0xFFFF.
Note: The prescaler counter is reset each time the contents of the SWTC field is loaded into the watchdog
Software watchdog enable. The WDT_SWCRR[SWEN] bit enables the WDT. This bit is set on reset, and can
be cleared by software after a system reset to disable the WDT. When the timer is disabled, the watchdog
counter and prescaler counter are held in a stopped state.
0 WDT disabled.
1 WDT enabled.
Software watchdog reset/interrupt select. This bit determines whether a WDT time out causes a hardware
reset or machine check interrupt to the core.
0 WDT causes an MCP interrupt to the core.
1 WDT causes a hardware reset.
Software watchdog counter prescale bit. Controls the divide-by-65,536 WDT counter prescaler.
0 The WDT counter is not prescaled.
1 The WDT counter clock is prescaled.
17
0
0
0
1
Figure 29-1. Software Watchdog Control Register (WDT_SWCRR)
counter due to executing a special service sequence or by executing a system reset.
18
0
0
0
2
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 29-2. WDT_SWCRR field descriptions
20
4
0
0
0
21
0
0
0
5
22
0
0
0
6
23
0
0
0
7
SWTC
Description
24
8
0
0
0
25
9
0
0
0
Figure
10
26
0
0
0
29-2, provides visibility to the
11
27
0
0
0
Software Watchdog Timer (WDT)
12
28
0
0
0
Access: User read/write
SWEN SWRI SWPR
1
13
29
0
1
14
30
0
0
15
31
29-3
0
0