MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 203

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
Freescale Semiconductor
Address
The reset values of COREDIS and AACKWS are determined from the reset configuration word.
Reset
Reset
PIPE_DEP
COREDIS
DTO_DIS
AACKWS
ATO_DIS
Field
W
W
R
R
:
Base + 0x00
16
0
0
0
0
0
Data time out detection disable.
0
1 Stop the DTO counter and prevent data time out detection.
Address time out detection disable.
0
1 Stop the ATO counter and prevent address time out detection.
This bit must always be cleared (set to 0).
Reserved. Write should preserve reset value.
Address acknowledge wait states. Specifies minimum number of address tenure wait states. This is the
minimum delay between assertion of TS and assertion of AACK.
00 AACK is asserted minimum 1 cycle after TS
01 AACK is asserted minimum 2 cycles after TS
10 AACK is asserted minimum 3 cycles after TS
11 AACK is asserted minimum 4 cycles after TS
Note: 00 option can be used only if the processor is not operating in 1:1 or 3:2 bus clock ratios
Pipeline depth (number of outstanding transactions).
000 Pipeline depth 1 (1 outstanding transaction)
001 Pipeline depth 2 (2 outstanding transactions)
010 Pipeline depth 3 (3 outstanding transactions)
011 Pipeline depth 4 (4 outstanding transactions)
Others Reserved
17
0
0
0
0
1
18
0
0
0
0
2
19
0
0
0
0
3
Figure 8-1. Arbiter Configuration Register (ACR)
MPC5125 Microcontroller Reference Manual, Rev. 2
20
0
0
0
0
4
Table 8-2. ACR field descriptions
DTO_
DIS
21
0
0
5
RPTCNT
ATO_
DIS
22
0
0
6
CORE
DIS
U
23
7
0
1
Description
24
0
0
0
0
8
PARK
W
25
0
0
0
9
U
AACKWS
10
26
0
APARK
1
U
11
27
0
1
CSB Arbiter and Bus Monitor
12
28
0
0
0
Access: User read/write
13
29
0
0
0
PARKM
PIPE_DEP
14
30
0
0
15
31
0
0
8-3