MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 433

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.3.1.4
The GPIO Interrupt Event Register (GPIO_GPIER) shown in
events that cause an interrupt. Each bit in the GPIO_GPIER register corresponds to an individual interrupt
source. GPIO_GPIER bits are cleared by writing 1s. Writing 0 has no effect.
16.3.1.5
The GPIO Interrupt Mask Register (GPIO_GPIMR) shown in
for the individual GPIO pins. When a masked interrupt occurs, the corresponding GPIO_GPIER bit is set,
regardless of the GPIO_GPIMR state. When one or more non-masked interrupt events occur, the GPIO
module issues an interrupt to the Power Architecture core.
Freescale Semiconductor
Address: Base + 0x0C
Reset
Reset
D[0:31]
D[0:31]
Field
Field
W
W
R
R
D16
D0
16
0
0
0
GPIO Interrupt Event Register (GPIO_GPIER)
GPIO Interrupt Mask Register (GPIO_GPIMR)
Bits D0–D31 of the GPIO_GPIER register in GPIO1 are set in response to
interrupt events occurring on the GPIO 00–31 pins. Bits D0–D31 of the
GPIO_GPIER register in GPIO2 are set in response to interrupt events
occurring on the GPIO 32–63 pins.
Data. Write data is latched and presented on external pins if GPIO_GPDIR has configured the GPIO pin as
an output. Read operation always returns the data at the pin.
Interrupt events. Indicates whether the interrupt event occurred on the corresponding GPIO pin.
0 No interrupt event occurred on the corresponding GPIO pin.
1 Interrupt event occurred on the corresponding GPIO pin.
D17
D1
17
0
0
1
D18
D2
18
0
0
2
Figure 16-5. GPIO Interrupt Event Register (GPIO_GPIER)
D19
D3
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 16-4. GPIO_GPDAT field descriptions
Table 16-5. GPIO_GPIER field descriptions
D20
D4
20
4
0
0
D21
D5
21
0
0
5
D22
D6
22
0
0
6
NOTE
D23
D7
23
0
0
7
Description
Description
D24
D8
24
8
0
0
Figure 16-5
Figure 16-6
D25
D9
25
9
0
0
D10
D26
10
26
0
0
carries information about the
defines the interrupt masking
D11
D27
11
27
0
0
D12
D28
12
28
General Purpose I/O (GPIO)
0
0
Access: User read/write
D13
D29
13
29
0
0
D14
D30
14
30
0
0
D15
D31
15
31
16-5
0
0