MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 1007

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
Freescale Semiconductor
0x1_1900–1_19FF
0x1_1A00–1_1EFF
0x1_1F00–1_1FFF
0x1_2000–1_3FFF
0x1_4000–1_57FF
0x1_5800–F_FFFF
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
This table provides the memory map.
Reserved locations are not guaranteed to be empty. Software should not access reserved locations.
from Module Base
(0xFF40_0000)
Address Offset
Offset from
0x004–0x01F
IMMRBAR
0x02C
0x03C
0x000
0x020
0x024
0x028
0x030
0x034
0x038
Chapter 2, “System Configuration and Memory Map (XLBMEN + Mem Map)”
MPC5125 Microcontroller Reference Manual, Rev. 2, Release Candidate
Internal Memory Map Base Address Register
(IMMRBAR)
Reserved
LocalPlus Boot Access Window register (LPBAW)
LocalPlus CS0 Access Window register (LPCS0AW)
LocalPlus CS1 Access Window register (LPCS1AW)
LocalPlus CS2 Access Window register (LPCS2AW)
LocalPlus CS3 Access Window register (LPCS3AW)
LocalPlus CS4 Access Window register (LPCS4AW)
LocalPlus CS5 Access Window register (LPCS5AW)
LocalPlus CS6 Access Window register (LPCS6AW)
Absolute offset
0xFF41_1A00
0xFF41_1F00
0xFF41_1900
0xFF41_2000
0xFF41_4000
0xFF41_5800
Table A-1. MPC5125 memory map (continued)
System Configuration (XLBMEN) 0xFF40_0000
Table A-2. MPC5125 Detailed Register Map
1
Programmable Serial Controller 9 (PSC9)
Reserved
Serial FIFO (SFIFO) for PSC 0 to 9
Reserved
DMA
Reserved
Register
Region Name
Chapter 2, “System Configuration and Memory
Access Reset Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
0xFF80_0000
See register
See register
See register
See register
See register
See register
See register
See register
description.
description.
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1
Chapter 25/25-1
Chapter 25/25-1
Section/Page
Chapter 9/9-1
2.2.5.1.1/2-5
2.2.5.1.3/2-8
2.2.5.1.4/2-9
2.2.5.1.4/2-9
2.2.5.1.4/2-9
2.2.5.1.4/2-9
2.2.5.1.4/2-9
2.2.5.1.4/2-9
2.2.5.1.4/2-9
Section/Page
Memory Map
A-3