MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 740

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PSC Centralized FIFO Controller (FIFOC)
26.2.1.2
26-6
ALARM LEVEL The alarm level defines the number of data bytes in the FIFO when the alarm status appears. Also, the
Address: Base + 0x84 (PSCn_TX_ALARM)
RESET SLICE Reset the FIFO slice.
SLICE_EN
Reset
Reset
DMA_EN
Field
Field
W
W
R
R
Base + 0xC4 (PSCn_RX_ALARM)
16
0
0
0
0
0
Alarm Level (ALARM)
0 Unused
1 Clears the underrun, overrun, and memory access error bits. Clears all data in the FIFO slice and reset the
Enable the request to the DMA engine
0 Request to the DMA engine is disabled.
1 Request to the DMA engine is enabled. The FIFO controller generates a request for this slice to DMA
Enable this Slice of the FIFO
0 FIFO slice is disabled. All interrupt and request lines are cleared. Access to the internal register is possible,
1 FIFO slice is enabled. The FIFO controller provides the data for the transmitter and stores the data from
interrupt lines to the core or the request lines to the DMA are asserted if these lines are enabled. For the TX
FIFO area, the alarm status appears if the number of data in the TX FIFO is below this alarm level. For the
RX FIFO area, the alarm status appears if the number of data in the RX FIFO is above this alarm level. The
alarm level and the request lines deassert if the number of data cross this level again.
17
0
0
0
0
1
internal pointer.
engine if this slice is enabled and the current data pointer reaches the alarm level.
but the PSC cannot read or write data to the FIFO.
the receiver. If the size of the FIFO slice is zero, it’s not possible to enable the FIFO.
18
0
0
0
0
2
19
0
0
0
0
3
Table 26-4. CMD field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 26-3. Alarm Level Register (ALARM)
Table 26-5. ALARM field descriptions
20
4
0
0
0
21
0
0
0
5
22
0
0
0
6
23
0
0
0
7
Description
Description
24
8
0
0
0
ALARM LEVEL
25
9
0
0
0
10
26
0
0
0
11
27
0
0
0
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0