MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 439

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.3.2.2
Figure 17-2
fields.
Freescale Semiconductor
Address: Base + 0x000
Reset
Reset
PRGD
SNSD
BUSY
Field
W
W
R
R
16
0
0
0
0
0
shows the bits in the Status IRQ Mask (IIM_STATM) register.
Status IRQ Mask (IIM_STATM) Register
Explicit Sense Cycle Done. Indicates that an explicit fuse sense cycle is done, and the data is available in the
Indicates whether the IIM is busy with a program or sense cycle. Any attempt to access the IIM registers other
than IIM_STAT while it is busy with a program or sense cycle (BUSY asserted) results in a bus error.
0 The IIM is not busy with a program or sense cycle.
1 The IIM is busy with a program or sense cycle.
Program Done. Indicates an e-Fuse program operation is done. Assertion causes an interrupt request if
PRGD_M is set in the status IRQ mask register.
This bit is automatically set by hardware upon completion of an e-Fuse program cycle; software must clear the
bit by writing 1 to it.
0 Program operation has not finished (read); no meaning (write).
1 Program operation has finished (read); clear bit (write).
IIM_SDAT register. Assertion causes an interrupt request if SNSD_M is set in the status IRQ mask register.
This bit is automatically set by hardware and must be cleared by software by writing 1 to it.
0 No explicit sense cycle has finished (read); no meaning (write).
1 An explicit sense cycle has finished (read); clear bit (write).
17
0
0
0
0
1
18
0
0
0
0
2
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 17-1. Status (IIM_STAT) Register
Table 17-2. IIM_STAT field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
BUSY
24
8
0
0
0
25
9
0
0
0
0
—
10
26
0
0
0
Table 17-3
—
11
27
0
0
0
Access: Supervisor read/write
—
12
28
0
0
0
describes the bit
—
13
29
0
0
0
PRGD SNSD
w1c
—
14
30
IIM/Fusebox
0
0
w1c
15
31
17-3
0
0
0