MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 174

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6.4.5.1
Only one BDLC module control bit is used when transmitting a message onto the SAE J1850 bus. This
bit, the Transmit End of Data (TEOD) bit, is set by the user to indicate to the BDLC module that the last
byte of that part of the message frame has been loaded into the BDLC Data Register. The TEOD bit,
located in BDLC Control Register 2, is also used when transmitting an In-Frame Response (IFR), but that
usage is described in
indicates to the BDLC module that the last byte written to the BDLC Data Register is the final byte to be
transmitted, and that following this byte a CRC byte and EOD symbol should be transmitted automatically.
Setting the TEOD bit also inhibits any further TDRE interrupts until TEOD is cleared. The TEOD bit is
cleared on the rising edge of the first bit of the transmitted CRC byte, or if an error or loss of arbitration is
detected on the bus.
6.4.5.1.1
The BDLC data register is a double-buffered register that handles the transmitted and received message
bytes. Bytes to be transmitted onto the SAE J1850 bus are written to the BDLC data register, and bytes
received from the bus by the BDLC module are read from the BDLC data register. Because this register is
double buffered, bytes written into it cannot be read by the CPU. If this is attempted, the read byte is the
last byte placed in the BDLC data register by the BDLC module, not the last byte written to the BDLC data
register by the CPU. For an illustration of the BDLC data register, refer to
Register (BDLC_DLCBDR).”
6.4.5.1.2
To transmit a message using the BDLC module, the user writes the first byte of the message to be
transmitted into the BDLC Data Register, initiating the transmission process. When the TDRE status
appears in the BDLC_DLCBSVR register, the user writes the next byte into the BDLC Data Register. After
all of the bytes have been loaded into the BDLC Data Register, the user sets the TEOD bit, and the BDLC
module completes the message transmission. What follows is an overview of the basic steps required to
transmit a message onto an SAE J1850 network using the BDLC module. For an illustration of this
sequence, refer to
6-38
1. Write the first byte into the BDLC data register.
To initiate a message transmission, the CPU simply loads the first byte of the message to be
transmitted into the BDLC Data Register. The BDLC module then performs the necessary bus
acquisition duties to determine when the message transmission can begin.
After the BDLC module determines that the SAE J1850 bus is free, a Start of Frame (SOF) symbol
is transmitted, followed by the byte written to the BDLC Data Register. After the BDLC module
readies this byte for transmission, the BDLC_DLCBSVR register reflects that the next byte can be
written to the BDLC Data Register (TDRE interrupt).
BDLC Transmission Control Bits
BDLC Data Register
Transmitting a Message with the BDLC
Due to the byte-level architecture of the BDLC module, the 12-byte limit on
message length as defined in SAE J1850 must be enforced by the user’s
software. The number of bytes in a message (transmitted or received) has no
meaning to the BDLC module.
Figure
Section 6.4.7, “Transmitting an In-Frame Response (IFR).”
6-20.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Section 6.3.2.4, “BDLC Data
Setting the TEOD bit
Freescale Semiconductor