MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 254

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
9.3
9.3.1
A typical initialization of the DMA would be:
After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The DMA_ENGINE reads the entire TCD for the selected
channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the
AHB bus unless a configuration error is detected. Transfers from the source (as defined by the source
address, TCD.SADDR) to the destination (as defined by the destination address, TCD.DADDR) continue
until the specified number of bytes (TCD.NBYTES) have been transferred. When the transfer is complete,
the DMA_ENGINE'S local TCD.SADDR, TCD.DADDR, and TCD.CITER are written back to the main
TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted,
further post processing is executed, such as interrupts, major loop channel linking, and scatter/gather
operations, if enabled.
9.3.2
The DMA performs various tests on the transfer control descriptor to verify consistency in the descriptor
data. Most programming errors are reported on a per-channel basis, with the exception of two errors, group
priority error (GPE) and channel priority error (CPE) in the DMAES register.
For all error types other than group or channel priority errors, the channel number causing the error is
recorded in the DMAES register. If the error source is not removed before the next activation of the
problem channel, the error is detected and recorded again.
The typical application enables error interrupts for all channels. You receive an error interrupt, but the
channel number for the DMAERR register and the error interrupt request line may be wrong because they
reflect the selected channel.
Channel priority errors are identified within a group after that group has been selected as the active group.
For example:
9-34
1. Write the DMACR register if a configuration other than the default is desired.
2. Write the channel priority levels into the DCHPRIn registers if a configuration other than the
3. Enable error interrupts in the DMAEEI registers if so desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the DMAERQ register.
6. Request channel service by either software (setting the TCD.START bit) or by hardware (slave
1. The DMA is configured for fixed-group and fixed-channel arbitration modes.
2. Group3 is the highest priority and all channels are unique in that group.
3. Group2 is the next highest priority and has two channels with the same priority level.
4. If Group3 has any service requests, those requests are executed.
default is desired.
device asserting its IPD_REQ signal).
Initialization/Application Information
DMA Initialization
DMA Programming Errors
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor