MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 205

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.2.1.3
The Arbiter Transfer Error Register (ATER) allows defining an event as a non-error event. If an event is
defined as a non-error event, an occurrence of the event is not reported in either the Arbiter Event register
(AER) or the event attributes and address register. For transfer types that are not defined as error events,
the arbiter also does not end address/data tenures.
Freescale Semiconductor
Address: Base + 0x08
Reset
Reset
Field
DTO
ATO
W
W
R
R
16
0
0
0
0
0
Arbiter Transfer Error Register (ATER)
Data time out. Specifies the time-out period for the data tenure. The granularity of this field is 128 bus clocks.
The maximum value is 8388480 coherent system bus clocks. Data time_out occurs, if the data tenure was not
ended before the specified time-out period timer expires between the assertion of DBB until the assertion of
last TA. When DTO = n, the timeout cycle is n × 128.
0x0000
0x0001
0x0002
0x0003
............................
0xFFFF
Address time out. Specifies the time-out period for the address tenure. The granularity of this field is 128 bus
clocks. Maximum value is 8388480 coherent system bus clocks. Address time-out occurs, if the address
tenure was not ended before the specified time-out period timer expires between assertion of TS signal until
the assertion of AACK signal. When ATO = n, the timeout cycle is n × 128.
0x0000
0x0001
0x0002
0x0003
............................
0xFFFF
17
0
0
0
0
1
18
0
0
0
0
2
Reserved
128 clock cycles
256 clock cycles
384 clock cycles
Reserved
128 clock cycles
256 clock cycles
384 clock cycles
8388480 clock cycles
8388480 clock cycles
Figure 8-3. Arbiter Transfer Error Register (ATER)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
Table 8-3. ATR field descriptions
21
0
0
0
0
5
22
0
0
0
0
6
Figure 8-3
23
0
0
0
0
7
Description
24
8
0
0
0
0
shows the fields of ATER.
25
9
0
0
0
0
ETEA RES ECW
10
26
0
0
1
11
27
0
0
1
CSB Arbiter and Bus Monitor
12
28
0
0
1
Access: User read/write
AO
13
29
0
0
1
DTO
14
30
0
0
1
ATO
15
31
0
0
1
8-5