MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 464

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18.2.1.6
The System Internal Interrupt Group C Priority Register (IPIC_SIPRR_C), shown in
the priority between the GPT10, GPT11, SDHC2, FEC1, FEC2, NFC, LPC, and SDHC1 internal interrupt
signals.
18-16
Address: Base + 0x18
SYSB1P–
Reset
Reset
SYSB0P
SYSB7P
Field
W
W
R
R
16
0
1
0
Figure 18-8. System Internal Interrupt Group C Priority Register (IPIC_SIPRR_C)
System Internal Interrupt Group C Priority Register (IPIC_SIPRR_C)
SYSC0P
SYSC4P
SYSB0 Priority order. Defines which interrupt source asserts its request in the SYSB0 priority position. The
user should not program the same code to more than one priority position (0–7). These bits can be changed
dynamically. The definition of SYSB0P is shown as follows:
000 FIFOC asserts its request in the SYSB0 position.
001 Reserved.
010 Reserved.
011 USB2OTG1 asserts its request in the SYSB0 position.
100 USB2OTG2 asserts its request in the SYSB0 position.
101 Reserved.
110 Reserved.
111 Reserved.
Same as SYSB0P, but for SYSB1P–SYSB7P.
17
0
0
1
18
0
0
2
19
0
1
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-8. IPIC_SIPRR_B field descriptions
SYSC1P
SYSC5P
20
4
0
0
21
0
1
5
22
0
1
6
SYSC2P
SYSC6P
23
0
1
7
Description
24
8
0
0
25
9
0
1
SYSC3P
SYSC7P
10
26
0
1
11
27
0
1
12
28
0
0
0
0
Freescale Semiconductor
Figure
Access: User read/write
13
29
0
0
0
0
18-8, defines
14
30
0
0
0
0
15
31
0
0
0
0