MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 245

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.1.16
When the fixed-priority channel arbitration mode is enabled (DMACR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel within a group. The channel priorities
are evaluated by numeric value (0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc.).
Software must program the channel priorities with unique values; otherwise, a configuration error is
reported. The range of the priority value is limited to the values of 0 through 15. When read, the GRPPRI
bits of the DCHPRIn register reflect the current priority level of the group of channels in which the
corresponding channel resides. GRPPRI bits are not affected by writes to the DCHPRIn registers. The
group priority is assigned in the DMACR. See
Channel preemption is enabled on a per channel basis by setting the ECP bit in the DCHPRIn register.
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of
starting a higher priority channel. After the preempting channel has completed all of its minor loop data
transfers, the preempted channel is restored and resumes execution. After the restored channel completes
one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting
service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption
(attempting to preempt a preempting channel) is not supported. After a preempting channel begins
execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected for
group and channel arbitration modes. See
1
2
9.2.1.17
Each channel requires a 32-byte transfer control descriptor (TCD) for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order. The definitions of
the TCD are presented as eight 32-bit values.
Freescale Semiconductor
GRPPRI[1:0]
GRPPRI[1:0] equals the corresponding group's GRPxPRI value of the DMACRn register.
CHPRI[3:0] defaults to the values for channel number (n) after reset.
Address: Base + 0x0100 + n
CHPRI[3:0]
Reset
Field
ECP
W
R
DMA Channel n Priority (DCHPRIn), n = [0,..., {15, 31, 63}
Transfer Control Descriptor (TCD)
ECP
Enable Channel Preemption
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
Channel n Current Group Priority. Group priority assigned to this channel group when fixed-priority arbitration
is enabled. These two bits are read only; writes are ignored.
Channel n Arbitration Priority. Channel priority when fixed-priority arbitration is enabled.
0
0
Figure 9-21. DMA Channel n Priority Register (DCHPRIn)
1
0
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 9-19. DCHPRIn field descriptions
—
2
GRPPRI[1:0]
1
Figure 9-21
Table 9-20
Figure 9-1
—
3
1
and
Description
is a 32-bit view of the basic TCD structure.
and
Table 9-19
Table 9-4
—
4
2
for the DCHPRIn definition.
for the DMACR definition.
—
5
2
CHPRI[3:0]
Direct Memory Access (DMA)
Access: User read/write
—
6
2
—
7
2
9-25