MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 370

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.3.5.3
The Interrupt Mask (ETH_IMASK) register provides control over which possible interrupt events are
allowed to generate an actual interrupt. All implemented bits in this CSR are read/write. This register is
cleared upon a hardware reset. If the corresponding bits in both the ETH_IEVENT and ETH_IMASK
registers are set, the interrupt is signalled to the CPU. The interrupt signal remains asserted until a 1 is
written to the ETH_IEVENT bit (write 1 to clear) or a 0 is written to the ETH_IMASK bit.
1
14-14
Address: Base + 0x008
COL_RETRY_
Reserved. Do not write. This bit must remain cleared.
LATE_COL
XFIFO_UN
Reset
Reset
GRAEN
EBERR
HBEEN
BREN
BTEN
Field
Field
LIM
W
W
R HBEE
R
16
N
0
0
0
0
Interrupt Mask (ETH_IMASK) Register
Ethernet bus error.
This bit indicates a system bus error occurred when a DMA transaction was underway. When the EBERR bit
is set, the ETHER_EN of the of the ETH_ECNTRL register is cleared, halting frame processing by the FEC.
Late collision.
This bit indicates a collision occurred beyond the collision window (slot time) in half-duplex mode. The frame
is truncated with a bad CRC and the remainder of the frame is discarded.
Collision retry limit.
This bit indicates a collision occurred on each of 16 successive attempts to transmit the frame. The frame is
discarded without being transmitted and transmission of the next frame commences. This situation can only
occur in half-duplex mode.
Transmit FIFO underrun.
This bit indicates the transmit FIFO became empty before the complete frame was transmitted. A bad CRC is
appended to the frame fragment and the remainder of the frame is discarded.
Heartbeat error interrupt enable
Babbling receiver interrupt enable
Babbling transmitter interrupt enable
Graceful stop interrupt enable
BRE
17
N
0
0
0
1
BTEN
18
0
0
0
2
Table 14-6. ETH_IEVENT field descriptions (continued)
GRA
Figure 14-4. Interrupt Mask Register (ETH_IMASK)
EN
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-7. ETH_IMASK field descriptions
TFIE
20
N
4
0
0
0
TBIE
21
N
0
0
0
5
RFIE
22
N
0
0
0
6
RBIE
23
N
0
0
0
7
Description
Description
MIIEN
24
8
0
0
0
EBER
REN
25
9
0
0
0
LCEN
10
26
0
0
0
CRLE
11
27
N
0
0
0
XFUN
EN
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
0
13
29
0
0
0
1
0
14
30
0
0
0
1
15
31
0
0
0
0