MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 477

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.2.1.17 System External Interrupt Polarity Check Register (IPIC_SEPCR)
Each bit in the System External Interrupt Polarity Check Register (IPIC_SEPCR), shown in
defines the polarity for each one of the external IRQn interrupt signals and determines whether the
corresponding IRQn signal is treated as active low or active high signal. The active low signals will assert
an interrupt request upon either a high-to-low change or assertion (low state) on the pin. The active high
signals will assert an interrupt request upon either a low-to-high change or assertion (high state) on the pin.
18.2.1.18 System Internal Interrupt Force Registers High and Low (IPIC_SIFCR_H
Each bit in the System Internal Interrupt Force Registers High and Low (IPIC_SIFCR_H and
IPIC_SIFCR_L), shown in
When a bit is set, the interrupt controller generates the corresponding interrupt (sets the corresponding
IPIC_SIPNRx bit).
The IPIC_SIFCRx registers can be read by the user at any time.
Freescale Semiconductor
Address: Base + 0x4C
Reset
Reset
Field
EIP0
EIP1
W
W
R
R
EIP0
16
0
0
0
0
and IPIC_SIFCR_L)
Figure 18-20. System External Interrupt Polarity Check Register (IPIC_SEPCR)
External Interrupt 0 Polarity. Defines the active state for the external IRQn interrupt signals.
0 Active Low.
1 Active High.
External Interrupt 1 Polarity. Defines the active state for the external IRQn interrupt signals.
0 Active Low.
1 Active High.
EIP1
17
0
0
0
1
18
0
0
0
0
2
Figure 18-21
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-21. IPIC_SEPCR field descriptions
20
4
0
0
0
0
21
0
0
0
0
and
5
Figure
22
0
0
0
0
6
18-22, corresponds to an internal interrupt source.
23
0
0
0
0
7
Description
24
8
0
0
0
0
Integrated Programmable Interrupt Controller (IPIC)
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
12
28
0
0
0
0
Access: User read/write
13
29
0
0
0
0
Figure
14
30
0
0
0
0
18-20,
18-29
15
31
0
0
0
0