MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 711

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.5.1.2
The supported UART Baud rate depends on the input frequency of the selected clock source, the selected
divide ratio and the selected sample rate. The clock source and the sample rate are defined in the
register. The divide ratio for the divider of the internal clock source is defined by concatenated
CTLR
Calculation of the UART Baud rate based on the internal clock:
Calculation of the UART Baud rate based on external MCLK:
Freescale Semiconductor
Signal
DCD
RxD
CTS
RTS
TxD
registers. For more information see
Transmitter Serial Data Output. TxD is held high (mark condition) when Tx is disabled, idle, or operating in the local
loop-back mode. Data is shifted out on TxD on the falling edge of the clock source, with the least significant bit (LSB)
sent first.
Receiver Serial Data Input. Data received on RxD is sampled on the rising edge of the clock source, with the LSB
received first.
Clear-to-Send. This input can generate an interrupt on a change of state.
Request-to-Send. This output can be programmed to be negated or asserted automatically by Rx or Tx. When
connected to a transmitter CTS, RTS can control serial data flow.
Data carrier detect Input. In the enhanced UART mode, this signal must be asserted during the data transmission.
UART Clock Generation
•
•
Asserted indicates a signal is active, independent of the voltage level
Negated indicates a signal is inactive.
Figure 25-40. Signal Configuration for a PSC/RS-232 Interface
Baud rate =
Baud rate =
Table 25-27. PSC Signal Description for UART Mode
MPC5125 Microcontroller Reference Manual, Rev. 2
PSC
sample rate x divider {CTUR:CTLR}
CTS
RTS
RxD
TxD
Figure
25-41.
sample rate
IPB Clock
Description
MCLK
Transceiver
DI2
DO2
DI1
DO1
RS-232
Programmable Serial Controller (PSC)
CTUR
Eqn. 25-1
Eqn. 25-2
CSR
25-33
and