MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 476

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18.2.1.16 System Error Mask Register (IPIC_SERMR)
Each bit in the System Error Mask Register (IPIC_SERMR), shown in
external and an internal mcp source. The user masks an MCP by clearing and enables an interrupt by
setting the corresponding IPIC_SERMR bit. When a masked MCP occurs, the corresponding
IPIC_SERSR bit is set regardless of the IPIC_SERMR bit, although no MCP request is passed to the core.
The IPIC_SERMR can be read by the user at any time.
18-28
Address: Base + 0x44
TEMP 125C
TEMP 125C
Reset
Reset
Field
IRQ0
WDT
Field
IRQ0
WDT
SBA
SBA
W
W
R
R
IRQ0 WDT
16
1
0
0
0
Each IPIC_SERSR bit corresponds to an external and an internal error source (MCP). When an error interrupt
signal is received, the interrupt controller sets the corresponding IPIC_SERSR bit.
IPIC_SERSR bits are cleared by writing ones to them. The unmasked event register bits should be cleared
before clearing of IPIC_SERSR. Because bits in this register can only be cleared, writing 0s to this register
has no effect.
IPIC_SERSR bits are reset only by power on reset. Soft and hard reset do not affect IPIC_SERSR bit states.
Each bit in the System Error Status Register (IPIC_SERMR), shown in
external and an internal MCP source. Mask an MCP by clearing and enables an interrupt by setting the
corresponding IPIC_SERMR bit. When a masked MCP occurs, the corresponding IPIC_SERSR bit is set,
regardless of the IPIC_SERMR bit, although no MCP request is passed to the core.
The IPIC_SERMR can be read by the user at any time.
17
1
0
0
1
SBA
18
1
0
0
2
Figure 18-19. System Error Mask Register (IPIC_SERMR)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-20. IPIC_SERMR field descriptions
Table 18-19. IPIC_SERSR field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
24
8
1
1
0
0
TEMP
125C
25
9
0
0
0
10
26
Figure
0
0
0
0
Figure
11
27
0
0
0
0
18-19, corresponds to an
18-19, corresponds to an
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
15
31
0
0
0
0