MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 487

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.3.4
The relative priority between as many as four internal and four external interrupts in each group is
programmable and can be changed dynamically. The group priorities are programmed in the IPIC mixed
interrupt priority registers (SMPRRx) and can be changed dynamically to implement a rotating priority.
In addition, the grouping of the locations of the mixed interrupt entries has the following two options:
18.3.5
In addition to the group relative priority option, IPIC_SICFR[HPI] can be used to specify one interrupt
source as having the highest priority. This interrupt remains within the same interrupt level as the other
interrupt controller interrupts, but is serviced before any other interrupt in
If the highest priority feature is not used, the IPIC selects the interrupt request in MIXA0 to be the highest
priority interrupt and the standard interrupt priority order is used from
be updated dynamically to allow changing a normally low priority source into a high priority-source for a
period as needed.
18.3.6
Each of the IPIC’s internal and external interrupt sources can independently assert one interrupt request to
the core.
flexibility exists in the relative ordering of the interrupts, but in general, relative priorities are as shown. A
single interrupt priority number is associated with each table entry.
Freescale Semiconductor
•
•
•
•
Grouped. In the group scheme, all interrupts are grouped together at the top of
of most other interrupt sources. This scheme is ideal for applications where all interrupt sources
function at a very high data rate and interrupt latency is very important.
Spread. In the spread scheme, priorities are spread over
lower interrupt latencies. This scheme is also programmed but cannot be changed dynamically.
Grouped. In the group scheme, all interrupts are grouped together at the top of the priority table,
ahead of most other interrupt sources. See
for applications where all interrupt sources function at a very high data rate and interrupt latency
is very important.
Spread. In the spread scheme, priorities are spread over the table so other sources can have lower
interrupt latencies. This scheme is also programmed but cannot be changed dynamically.
Table 18-28
Mixed Interrupts Group Relative Priority
Highest Priority Interrupt
Interrupt Source Priorities
Priority Level
shows the prioritization of these interrupt sources. As described in previous sections,
0
1
2
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-28. Interrupt Source Priority Levels
Interrupt Source Description
MIXA0 (Grouped)
MIXA1 (Grouped)
MIXA0 (Spread)
Highest
Table 18-28
for more information. This scheme is ideal
Table 18-28
Integrated Programmable Interrupt Controller (IPIC)
Yes (No for ext. interrupts)
Yes (No for ext. interrupts)
Yes (No for ext. interrupts)
Table
Multiple Events
Table
18-28. IPIC_SICFR[HPI] can
so other sources can have
—
18-28.
Table
18-28, ahead
18-39