MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 640

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NAND Flash Controller (NFC)
23.7.4
23-10
CHIP_SEL_RB[3:0] The field CHIP_SEL determines which NFC_CE line will go low, the field CHIP_SEL_RB determines to
Address: Base + 0x3F0C
ROW_ADDR1[7:0] First byte of row address.
ROW_ADDR2[7:0] Second byte of row address.
ROW_ADDR3[7:0] Third byte of row address.
COL_ADDR1[7:0]
COL_ADDR2[7:0]
CHIP_SEL[3:0]
Reset
Reset
W
W
R
R
Field
Field
16
0
0
0
Row Address register (ROW_ADDR)
CHIP_SEL_RB[3:0]
17
0
0
1
0 Corresponding NFC_CE is disabled.
1 Corresponding NFC_CE is enabled.
which NFC_R/B lines will be waited on a wait for R/B command. Normally, when 4 NFC_CE lines and 4
NFC_R/B lines are used, the two fields must contain identical values. When 4 NFC_CE lines, and 1
NFC_R/B line is used, then CHIP_SEL is the true chip select, and CHIP_SEL_RB is always 1.
Chip select - Bit mask to enable/disable each of the four chip selects.
First byte of column address.
Second byte of column address.
18
0
0
2
ROW_ADDR2[7:0]
Figure 23-6. Row Address register (ROW_ADDR)
19
1
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 23-7. ROW_ADDR field descriptions
Table 23-6. COL_ADDR field descriptions
20
4
0
0
CHIP_SEL[3:0]
21
0
0
5
22
0
0
6
23
1
0
7
Description
Description
24
8
0
0
25
9
0
0
10
26
0
0
ROW_ADDR3[7:0]
ROW_ADDR1[7:0]
11
27
0
0
12
28
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
14
30
0
0
15
31
0
0