MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 789

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.3.2.10 SDHC Interrupt Control (SDHC_INT_CNTR) Register
When certain events occur in the module, the SDHC has the ability to set an interrupt as well as set
corresponding status register bits. The SDHC Interrupt Control (SDHC_INT_CNTR) register allows
control over whether these interrupts should be recognized. Interrupts are ORed to provide a single
interrupt IPI_IRQ to the system. Software must read the status to determine the source of the event.
Figure 28-11
Freescale Semiconductor
Address: Base + 0x20
Address: Base + 0x24
REVISION
Reset
Reset
Reset
Reset
NUMBER
Field
W
W
W
W
R
R
R
R CARD_
INSERTI
ON_EN
16
16
0
0
0
0
0
0
0
0
shows the SDHC_INT_CNTR register and
CARD_
REMOV
Revision Number. Specifies revision number of the MMC/SD module. This is fixed at 0x0000_0400.
AL_EN
17
17
0
0
0
0
0
0
1
1
Figure 28-11. SDHC Interrupt Control (SDHC_INT_CNTR) Register
Figure 28-10. SDHC Revision Number (SDHC_REV_NO) Register
SDIO_
IRQ_
EN
18
18
0
0
0
0
0
0
2
2
DAT0_
EN
19
19
0
0
0
0
0
0
3
3
Table 28-12. SDHC_REV_NO field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
20
20
4
0
0
0
4
0
0
0
0
21
21
0
0
1
0
0
0
0
5
5
22
22
0
0
0
0
0
0
0
6
Revision Number[15:0]
6
23
23
0
0
0
0
0
0
0
7
7
Description
Table 28-13
24
24
8
0
0
0
8
0
0
0
0
25
25
9
0
0
0
9
0
0
0
0
describes the bit fields.
10
26
10
26
0
0
0
0
0
0
0
Secure Digital Host Controller (SDHC)
READ
BUF_
_EN
11
27
11
27
0
0
0
0
0
0
BUF_
E_EN
WRIT
12
28
12
28
0
0
0
0
0
0
Access: User read/write
Access: User read-only
END_
_RES
CMD
13
29
13
29
0
0
0
0
0
0
WRITE
DONE
_OP_
14
30
14
30
0
0
0
0
0
0
DONE
READ
_OP_
28-17
15
31
15
31
0
0
0
0
0
0