MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 888

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.5.2
The asynchronous transfer list (based at the USB_ASYNCLISTADDR register) is where all the control
and bulk transfers are managed. Host controllers only use this list when it reaches the end of the periodic
list, the periodic list is disabled, or the periodic list is empty.
The asynchronous list is a simple circular list of queue heads. The USB_ASYNCLISTADDR register is a
pointer to the next queue head. This implements a pure round-robin service for all queue heads linked into
the asynchronous list.
32.5.3
The format of an isochronous transfer descriptor is illustrated in
for high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous
TDs must be aligned on a 32-byte boundary.
32-60
Asynchronous List Queue Head Pointer
Isochronous (High-Speed) Transfer Descriptor (iTD)
USB_ASYNCLISTADDR
Operational
Registers
Figure 32-45. Asynchronous Schedule Organization
Typ
00
01
10
11
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-43. Typ Field Encodings
Isochronous Transfer Descriptor
Queue Head
Split Transaction Isochronous Transfer Descriptor
Frame Span Traversal Node.
H
Bulk/Control Queue Heads
Description
Figure
32-46. This structure is used only
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