MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 385

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3.5.21 FIFO Receive Bound(ETH_R_BOUND) Register
The FIFO Receive Bound (ETH_R_BOUND) register can be read to determine the upper address bound
of the FIFO RAM. The highest address of FIFO_RAM is R_BOUND – 1.Drivers can use the value of
R_BOUND, along with the ETH_R_FSTART[R_FSTART] register value, to appropriately divide the
available FIFO RAM between the transmit and receive data paths.
The ETH_R_BOUND register is read-only.
Freescale Semiconductor
Address: Base + 0x144
Address: Base + 0x14C
Reset
Reset
X_WMRK
Reset
Reset
Field
W
W
W
W
R
R
R
R
16
16
0
0
0
0
0
0
0
0
0
0
Transmit FIFO watermark. Frame transmission begins when the number of bytes selected by this field have
been written into the transmit FIFO if an end-of-frame has been written to the FIFO or if the FIFO is full before
the selected number of bytes have been written. The options are:
0X 64 bytes written to xFIFO
10 128 bytes written to xFIFO
11 192 bytes written to xFIFO
17
17
0
0
0
0
0
0
0
0
1
1
Figure 14-21. FIFO Transmit FIFO Watermark (ETH_X_WMRK) Register
Figure 14-22. FIFO Receive Bound (ETH_R_BOUND) Register
18
18
0
0
0
0
0
0
0
0
2
2
19
19
0
0
0
0
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-25. ETH_X_WMRK field descriptions
20
20
4
0
0
0
0
4
0
0
0
0
21
21
0
0
0
0
0
0
1
1
5
5
22
22
0
0
0
0
0
0
1
6
6
23
23
0
0
0
0
0
0
0
7
7
Description
24
24
8
0
0
0
0
8
0
0
0
R_BOUND
25
25
9
0
0
0
0
9
0
0
0
10
26
10
26
0
0
0
0
0
0
0
11
27
11
27
0
0
0
0
0
0
0
Fast Ethernet Controller (FEC)
12
28
12
28
0
0
0
0
0
0
0
Access: User read/write
Access: User read-only
13
29
13
29
0
0
0
0
0
0
0
X_WMRK
14
30
14
30
0
0
0
0
0
0
0
14-29
15
31
15
31
0
0
0
0
0
0
0