MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 616

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MSCAN
FIFO
Architecture
the RXFIF flag to acknowledge the interrupt, and release the foreground buffer. A new message, which
can follow immediately after the IFS field of the CAN frame, is received into the next available RxBG. If
the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors etc.), the actual
contents of the buffer are over-written by the next message. The buffer is not shifted into the FIFO.
When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the
background receive buffer (RxBG), but does not shift it into the receiver FIFO, generate a receive
interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loop back
mode
messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages
in the event that it loses arbitration
receiver.
An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly
received messages with accepted identifiers and another message is correctly received from the bus with
an accepted identifier. The latter message is discarded and an error interrupt with overrun indication is
generated if enabled
while the receiver FIFO is being filled, but all incoming messages are discarded. As soon as a receive
buffer in the FIFO is available again, new valid messages are accepted.
22.4.3
The MSCAN identifier acceptance registers
Register
ID28–ID0). Any of these bits can be marked “don’t care” in the MSCAN identifier mask registers. See
Section 22.3.2.17, “MSCAN Identifier Mask Register (CANIDMR0–CANIDMR7).”
A filter hit is indicated to the application software by a set receive buffer full flag (RXF = 1) and 3 bits in
the CANIDAC register. See
(CANIDAR0–CANIDAR7).”
caused the acceptance. They simplify the application software’s task to identify the cause of the receiver
interrupt. In case more than one hit occurs (two or more filters match), the lower hit has priority.
A flexible programmable generic identifier acceptance filter has been introduced to reduce the Power
Architecture interrupt loading. The filter is programmable to operate in four different modes
1. Only if the RXF flag is not set.
2. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.
3. Reference the Bosch CAN 2.0A/B protocol specification dated September 1991 for details.
4. For a better understanding of references made within the filter mode description, reference the Bosch specification dated
22-38
September 1991 which details the CAN 2.0A/B protocol.
•
1
Section 22.3.2.2, “MSCAN Control 1 Register (CANCTL1),”
, and generates a receive interrupt (see
Two identifier acceptance filters, each to be applied to:
— The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame:
(CANIDAC)”) define the acceptable patterns of the standard or extended identifier (ID10–ID0 or
– Remote transmission request (RTR)
– Identifier extension (IDE)
Identifier Acceptance Filter
2
by set RXFIF. The receive manager has to read the received message from the RxFG, reset
Section 22.4.11.4, “Error Interrupt.”
Section 22.3.2.16, “MSCAN Identifier Acceptance Register
MPC5125 Microcontroller Reference Manual, Rev. 2
These identifier hit flags (IDHIT2–0) clearly identify the filter section that
3
. If arbitration is lost, the MSCAN must be prepared to become a
(Section 22.3.2.12, “MSCAN Identifier Acceptance Control
Section 22.4.11.2, “Receive
The MSCAN remains able to transmit messages
where the MSCAN treats its own
Interrupt”) to the Power
Freescale Semiconductor
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