MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 725

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

serial clock. As long as the RX FIFO becomes not full and the TX FIFO becomes not empty, the transfer
is ongoing.
In SPI slave mode, the MCLK must be running/enabled even though it is not used to generate the serial
clock SCK, which is provided by the external master SPI device. The frequency of MCLK is not critical,
as long as it is faster than the SCK frequency.
Table 25-35
Table 25-36
Freescale Semiconductor
Register
CTUR
CTLR
SICR
CCR
CR
CR
•
•
•
•
•
•
•
Tx FIFO
Enable
Empty
32-bit data
Clock is active high, CPOL = 0
The first SCK edge is issued one half cycle into the data transfer; CPHA = 0
MSB first
Baud rate 1 Mbit/s
DSCLK delay = 0.5 µs
DTL delay = 2.0 µs
MOSI
MISO
SCK
SS
Tx
0x0F00_C000 Select the 32bit Codec SPI master mode, MSB first, CPOL = 0,CPHA = 0
shows an example of how to configure the PSC3 as SPI master.
shows an example of how to configure the PSC2 as SPI slave.
0x070F
Value
0x0A
0x00
0x84
0x05
Disable the Tx and Rx part for configuration if the PSC was enabled by the work before.
Set the SCK and DSCKL delay
Set the DTL delay 2us
Enable Tx and Rx
DSCKl
The PSC starts to generate the SCK if the transmitter is enabled
and the Tx FIFO is not empty!
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 25-35. 32-bit SPI Master Mode for PSC3
Figure 25-50. SPI Parameter
Setting
Programmable Serial Controller (PSC)
DTL
Next
Frame
25-47