MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 650

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NAND Flash Controller (NFC)
Page size supported is 512 bytes, 2 KB, 4 KB, and 8 KB. Eight different ECC settings are provided: 0-, 4-,
6-, 8-, 12-, 16-, 24-, and 32-bit errors. They use 0, 8, 12, 15, 23, 30, 45, or 60 ECC bytes. ECC works on
page sizes of 512 + spares bytes, 1 KB + spares bytes, and 2 KB + spares bytes. The ECC algorithm used
is a BCH code.
ECC is performed on the fly, during both read and write.
The error corrector can write ECC status to the spare area. This is done because the read is pipelined. This
means, while current page is being transferred from flash to buffer, previous page is ECC corrected, and
the page before that is being transferred using DMA. The following method has been devised to inform
the CPU of ECC errors. The ECC status is written to the aux area of the sector and transferred to memory.
See
Section 23.8.1, “Error Corrector Status,”
for more information. The CPU must inspect the ECC result
in memory, and act appropriately.
Reads are pipelined, as already described. Writes are not pipelined. Write is flow-through, and no advance
operations are done during write. If a problem is found during write, the command sequence may be
interrupted, and the CPU is informed.
Each page read, page write, page erase, read ID, or read status command sequence needs CPU attention
only once. The CPU needs to prepare the DMA to point to the data, write correct values to all registers,
and start the command. After command completion, the NFC may interrupt the CPU.
The NFC allows command repeat. Command repeat is useful for writes, reads, and erases, and allows
processing multiple pages with just one command given by the CPU. No bank interleaving is supported
during command repeat.
After power-on reset, a reset command (0xFF) is sent to the flash.
Boot from NAND flash is optional. The feature is activated when boot_after_reset input is high during
power-on reset. If boot feature is activated, the NFC will read 4 pages from block 0. Each page is 1056
bytes. The boot pages are protected by 32-bit error correction, which means that of the 1056 bytes, 996
bytes are user bytes, and 60 bytes are ECC bytes. When the data from the boot pages is read, successfully
error corrected, and stored in the NFC SRAM, the flag boot_done is pulled high, indicating to the CPU
that its boot code is visible in the NFC SRAM, and visible on addresses 0 to 3983 (decimal) (3984 bytes
total).
In case the boot image from sector 0 cannot be corrected, because there are more than 32 errors in one or
several pages, boot is retried on the blocks at row addresses 256, 512, and 768. If it still fails after these
retries, the boot_fail flag is pulled high, and boot is given up.
Right after boot, a special address hashing function is active on all reads and writes done to NFC SRAM.
This hashing function interleaves the page data from the 4 boot pages in such a way that all user data is
visible in address range 0 to 3983 instead of four different ranges, each for one page. This hashing is
controlled by the FLASH_CONFIG[BOOT_MODE] bit, and the hashing should be turned off by the CPU
after finishing reading/executing the boot image, and before normal operations of the NFC. Reference
Figure 23-25
and
Section 23.5, “NFC Buffer Memory Space.”
Page size at boot is set to 1056 bytes, to be compatible with a large number of NFC devices, without
needing additional power-on reset flags to indicate boot device.
•
Compatible with 8-wide SLC and MLC devices with page size of 2048 bytes + 64 bytes spare
MPC5125 Microcontroller Reference Manual, Rev. 2
23-20
Freescale Semiconductor