MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 801

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A summary of events that take place when a SDIO card generates an interrupt is detailed in this section.
When an SDIO card generates an interrupt request, it sets its interrupt pending bit in the CSR register and
asserts the interrupt line, which is shared with DAT1 line in 4-bit mode. The SDHC detects and steers the
card’s interrupt to the selected IRQ line of the interrupt controller.
28.4.4
28.4.4.1
In this case, the DAT1 pin is dedicated to providing the interrupt function. Pulling the DAT1 low asserts
an interrupt until the host clears the interrupt.
28.4.4.2
Because the interrupt and data line 1 share pin DAT1 in 4-bit mode, an interrupt is only sent by the card
and recognized by the host during a specific time. This is known as the interrupt period. The SDHC
samples only the level on DAT1 during the interrupt period. At all other times, the host interrupt controller
ignores the level on DAT1. The definition of the interrupt period is different for operations with single
block and multiple block data transfers.
In the case of normal single data block transmissions, the interrupt period becomes active two clock cycles
after the completion of a data packet. This interrupt period lasts until after the card receives the end bit of
the next command with a data block transfer associated with it.
Freescale Semiconductor
IPG_CLK
Application
SDIO Card Interrupt
Bus
Interrupts in 1-Bit Mode
Interrupt in 4-Bit Mode
Post-Processor
Register
Handler
DATA from
Figure 28-20. Memory Controller Block Diagram
MPC5125 Microcontroller Reference Manual, Rev. 2
Configuration
Operation
SDIO-ReadWait
Pause
Data
Logic
Card Detection
Interrupter
Operation
SDIO-IRQ
Circuitry
Resume
&
Memory Controller
Command
Response
Circuitry
Secure Digital Host Controller (SDHC)
Interrupt
Handler
sdhc_irq
Post-Processor
CMD from
28-29