MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 804

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
28.4.6
When there is no operation between SDHC and the card through SD bus, disable the ipg_clk and
SDHC_CLK in chip level clock control module to save power. When you need to use SDHC to
communicate with the card, enable the clock.
28.4.7
There is one clock divider and one clock prescaler in SDHC to divide the high frequency input clock
SDHC_CLK to a lower frequency clock, which most of the SDHC logic can use. See
details about clocks used in SDHC. The input clock first goes through a 4-bit divider and then a 12-bit
prescaler to generate a clock named CLK_20M. This clock is used internally by SDHC and generates the
MMC_SD_CLK. The MMC_SD_CLK to the card has the same clock frequency as CLK_20M.
CLK_20M is derived from the CLK_DIV by using the 12-bit prescaler. The CLK_DIV is derived from the
input clock SDHC_CLK by using the 4-bit divider. SDHC clock rate register controls the divide rate for
both the divider and the prescaler. Refer to
Register,”
28-32
for the clock rate register information.
Power Management
System Clock Controller
Send a command (CMD42 for SDMem or CMD52 for SDIO) to the card to
disable the card internal pull-up resistor after card detection and
identification. Because the SD protocol requires the DAT line must be
pulled up for data transfer, disable the host side of the DAT3 pull-down
feature and configure it as pull-up. If the card internal pull-up resistor is
disabled during this, the card removal interrupt cannot be detected through
DAT3.
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 28.3.2.3, “SDHC Clock Rate (SDHC_CLK_RATE)
NOTE
Freescale Semiconductor
Figure 28-22
for