MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 87

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 4
Reset
4.1
The MPC5125 has three reset flows, PORESET, HRESET, and SRESET. These flows can be initiated by
the following events:
Table 4-1
1. The JTAG initiated reset (power on reset, hardware reset, and soft reset) is independent of the reset state of the JTAG controller
2. The Reset Control Register may initiate a SRESET or HRESET sequence. see
Freescale Semiconductor
(TRST)
PORESET
•
•
•
•
•
•
•
•
•
HRESET
SRESET
Power on reset (PORESET)
Hard reset (HRESET)
Soft reset (SRESET)
JTAG reset command
Checkstop (MCP) event
PLL unlock event
Watchdog timer (WDT) module
Bus monitor
Software write to Reset Control Register (RCR)
Introduction
summarizes each peripheral and the relation to each reset flow.
Peripheral
CLOCK
Latch
RST_CONF
BDLC
1
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 4-1. Peripheral Versus Reset
Figure 4-1. Internal Reset Flow
HRESET
Flow
HRESET
—
2
x
1
Section 4.6.6, “Reset Control Register (RCR).”
SRESET
Flow
SRESET
—
x
Done
4-1