MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 456

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18.2.1.2
The System Global Interrupt Vector Register (IPIC_SIVCR), shown in
(Table
Table 18-4
18-8
Address: Base + 0x04
Reset
Reset
Field
HPIT
Field
IVEC
W
W
R
R
18-3) representing the unmasked interrupt source of the highest priority level.
16
0
0
0
0
0
shows the definition of IVEC.
System Global Interrupt Vector Register (IPIC_SIVCR)
Interrupt vector numbers are assigned to each module and cannot be
changed. For example, the SDHC2 module always returns 0x000_0011 as
its interrupt vector regardless of its relative priority in the SYSC group.
HPI Priority Position IPIC Output Interrupt Type. Defines type of the IPIC output interrupt signal (int, cint, or
smi) asserts its request to the core in the HPI priority position. These bits cannot be changed dynamically. If
S/W really wants to change it, it has to make sure the corresponding interrupt source is masked or it won’t
happen during the change.
The definition of HPIT is as follows:
00 int request is asserted to the core for HPI.
01 smi request is asserted to the core for HPI.
10 cint request is asserted to the core for HPI.
11 Reserved.
Interrupt Vector. Specifies a 7-bit unique number of the IPIC’s highest priority interrupt source, pending to the
core. When an interrupt request occurs, IPIC_SIVCR can be read. If there are multiple interrupt sources,
IPIC_SIVCR latches the highest priority interrupt.
Note: The value of SIVEC cannot change while it is being read.
Note: While the upper 24 bits of this register are set to zero at the release of PORESET, they can and will
17
0
0
0
0
1
Figure 18-3. System Global Interrupt Vector Register (IPIC_SIVCR)
change during device operation. Therefore, when using the value of the IVEC field, be sure to mask off
the upper 24 bits of this register.
18
0
0
0
0
2
Table 18-2. IPIC_SICFR field descriptions (continued)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-3. IPIC_SIVCR field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
NOTE
23
0
0
0
0
7
Description
Description
24
8
0
0
0
0
25
9
0
0
0
Figure
10
26
0
0
0
11
27
0
0
0
18-3, contains a 7-bit code
IVEC
12
28
0
0
0
Freescale Semiconductor
Access: User read-only
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0